公开(公告)号：US20080239833A1

公开(公告)日：2008-10-02

申请号：US11731766

申请日：2007-03-30

申请人： Thomas Nirschl ,  Jan Otterstedt

发明人： Thomas Nirschl ,  Jan Otterstedt

IPC分类号： G11C7/06

CPC分类号： G11C11/5642 ,  G11C16/32 ,  G11C2211/5634

摘要： A multi-level sensing scheme compares the state of a multi-level storage cell with monotonously changing reference states, which are associated to different information values. That particular information value is identified to be the information stored in the multi-level storage cell, which has associated that reference state which, in a changing direction, firstly exceeds the state.

摘要翻译： 多级感测方案将多级存储单元的状态与单调变化的参考状态进行比较，其与不同的信息值相关联。 该特定信息值被识别为存储在多级存储单元中的信息，其与改变方向上首先超过该状态的参考状态相关联。

公开(公告)号：US07327593B2

公开(公告)日：2008-02-05

申请号：US11284092

申请日：2005-11-22

申请人： Martin Ostermayr ,  Thomas Nirschl

发明人： Martin Ostermayr ,  Thomas Nirschl

IPC分类号： G11C17/00

CPC分类号： G11C17/12 ,  H01L27/112 ,  H01L27/11266

摘要： The invention relates to a ROM memory cell of a ROM memory, which provides a first predetermined potential or a second predetermined potential in the driven state at a memory cell output in a manner dependent on the programming state of the ROM memory cell.

摘要翻译： 本发明涉及一种ROM存储器的ROM存储器单元，其以取决于ROM存储器单元的编程状态的方式在存储单元输出处以驱动状态提供第一预定电位或第二预定电位。

公开(公告)号：US07292466B2

公开(公告)日：2007-11-06

申请号：US11324700

申请日：2006-01-03

申请人： Thomas Nirschl

发明人： Thomas Nirschl

IPC分类号： G11C11/00

CPC分类号： G11C13/0064 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

摘要： A memory includes a first resistive memory cell, a current source configured to provide an input current indicating a desired resistance level for the first memory cell, and a current mirror that mirrors the input current to provide an output current. The memory includes a first switching circuit configured to pass the output current to the first memory cell with the first memory cell not at the desired resistance level, and block the output current from the first memory cell in response to the first memory cell achieving the desired resistance level.

摘要翻译： 存储器包括第一电阻存储器单元，被配置为提供指示第一存储单元的期望电阻电平的输入电流的电流源以及镜像输入电流以提供输出电流的电流镜。 存储器包括第一切换电路，其被配置为使得第一存储器单元不处于期望的电阻电平时将输出电流传递到第一存储器单元，并且响应于第一存储器单元实现期望的阻塞来阻止来自第一存储器单元的输出电流 阻力水平。

公开(公告)号：US20070034920A1

公开(公告)日：2007-02-15

申请号：US11493252

申请日：2006-07-26

申请人： Thomas Nirschl ,  Alexander Olbrich ,  Martin Ostermayr

发明人： Thomas Nirschl ,  Alexander Olbrich ,  Martin Ostermayr

IPC分类号： H01L29/94

CPC分类号： H01L27/10888 ,  H01L27/108 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/90

摘要： A semiconductor memory cell and production method provides a storage capacitor connected to a selection transistor. The storage capacitor is formed as a contact hole capacitor in at least one contact hole for a source or drain region. Such a semiconductor memory cell can be produced cost-effectively and allows a high integration density.

摘要翻译： 半导体存储单元和制造方法提供连接到选择晶体管的存储电容器。 存储电容器在至少一个用于源极或漏极区域的接触孔中形成为接触孔电容器。 可以成本有效地制造这种半导体存储单元并且允许高的集成密度。

公开(公告)号：US09389999B2

公开(公告)日：2016-07-12

申请号：US13587993

申请日：2012-08-17

申请人： Thomas Kern ,  Jens Rosenbusch ,  Ulrich Backhausen ,  Edvin Paparisto ,  Thomas Nirschl

发明人： Thomas Kern ,  Jens Rosenbusch ,  Ulrich Backhausen ,  Edvin Paparisto ,  Thomas Nirschl

IPC分类号： G06F12/00 ,  G06F12/02 ,  G11C16/10

CPC分类号： G06F12/0246 ,  G06F2212/1044 ,  G06F2212/7202 ,  G11C16/105

摘要： The invention relates to an electronic memory system, and more specifically, to a system for emulating an electrically erasable programmable read only memory in a non-volatile memory device, and a method of emulating an electrically erasable programmable read only memory in a non-volatile memory device. According to an embodiment, a system for emulating an electrically erasable programmable read only memory is provided, the system including a Flash memory, wherein the Flash memory is configurable into a first region and a second region, wherein the first region is adapted to store a first class of data and the second region is adapted to store a second, different class of data.

摘要翻译： 本发明涉及一种电子存储器系统，更具体地说，涉及用于在非易失性存储器件中仿真电可擦除可编程只读存储器的系统，以及一种以非易失性存储器模拟电可擦除可编程只读存储器的方法 存储设备。 根据实施例，提供了一种用于模拟电可擦除可编程只读存储器的系统，该系统包括闪存，其中闪存可配置成第一区域和第二区域，其中第一区域适于存储 第一类数据和第二区域适于存储第二种不同类别的数据。

公开(公告)号：US08389973B2

公开(公告)日：2013-03-05

申请号：US12975997

申请日：2010-12-22

申请人： Thomas Nirschl

发明人： Thomas Nirschl

IPC分类号： H01L45/00

CPC分类号： H01L29/7391 ,  H01L27/228 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

摘要： A memory includes a first tunneling field effect transistor including a first drain and a first source, the first drain coupled to a first resistive memory element. The memory includes a second tunneling field effect transistor including a second drain and sharing the first source, the second drain coupled to a second resistive memory element. The memory includes a first region coupled to the first source for providing a source node.

摘要翻译： 存储器包括第一隧道场效应晶体管，其包括第一漏极和第一源极，第一漏极耦合到第一电阻存储器元件。 存储器包括第二隧道场效应晶体管，其包括第二漏极并共享第一源极，第二漏极耦合到第二电阻存储器元件。 存储器包括耦合到第一源的第一区域，用于提供源节点。

公开(公告)号：US20120300566A1

公开(公告)日：2012-11-29

申请号：US13113427

申请日：2011-05-23

申请人： David Mueller ,  Thomas Nirschl

发明人： David Mueller ,  Thomas Nirschl

IPC分类号： G11C7/12

CPC分类号： G11C7/065 ,  G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18

摘要： Some embodiments of the present disclosure relate to a sense amplifier architecture that facilitates fast and accurate read operations. The sense amplifier architecture includes a folded cascode amplifier for its first sense amplifier stage, and a pre-charge circuit to establish a pre-charge condition for a senseline and a reference senseline of the sense amplifier. The pre-charge circuit and the folded cascode amplifier each include one or more cascode transistors of the same size and which receive the same bias voltage on a gate thereof. This architecture provides fast and accurate read operations in a relatively small footprint, thereby providing a good blend of cost and performance.

摘要翻译： 本公开的一些实施例涉及促进快速和准确的读取操作的读出放大器架构。 感测放大器架构包括用于其第一读出放大器级的折叠共源共栅放大器和用于为感测放大器的感测线和参考感测线建立预充电状态的预充电电路。 预充电电路和折叠共源共栅放大器各自包括相同尺寸的一个或多个共源共栅晶体管，并且在其栅极上接收相同的偏置电压。 该架构在相对较小的占地面积中提供快速准确的读取操作，从而提供了成本和性能的良好组合。

公开(公告)号：US08159857B2

公开(公告)日：2012-04-17

申请号：US12563427

申请日：2009-09-21

申请人： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer

发明人： Berndt Gammel ,  Thomas Nirschl ,  Gerd Dirscherl ,  Philip Schlazer

IPC分类号： G11C11/00

CPC分类号： G11C13/0059 ,  G11C13/0004 ,  G11C13/0069

摘要： One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state.

摘要翻译： 一个或多个实施例涉及包括电路和可编程电阻元件的电子设备。 可编程电阻元件包括第一和第二状态，其中可编程电阻元件被配置为允许响应于包括至少预定义电平的信号从第二状态切换到第一状态。 该电路被配置为提供上述预定义电平的信号，其中电路被配置为向可编程电阻元件提供开关信号，其中开关信号引起从第一状态切换到第二状态。

公开(公告)号：US08125821B2

公开(公告)日：2012-02-28

申请号：US11756639

申请日：2007-06-01

申请人： Jan Otterstedt ,  Thomas Nirschl ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

发明人： Jan Otterstedt ,  Thomas Nirschl ,  Christian Peters ,  Michael Bollu ,  Wolf Allers ,  Michael Sommer

IPC分类号： G11C11/00

CPC分类号： G11C13/004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/15 ,  G11C2213/79

摘要： One or more embodiments are related to a method of operating a phase-change memory array, including: providing the phase-change memory array, the phase-change memory array including a phase-change memory element in series with an access device between a first address line and a power line; causing a first current through the memory element from the first address line to the power line; and causing a second current through the memory element from the power line to the first address line.

摘要翻译： 一个或多个实施例涉及一种操作相变存储器阵列的方法，包括：提供相变存储器阵列，所述相变存储器阵列包括与存取装置串联的相变存储器元件，位于第一 地址线和电力线; 引起从第一地址线到电力线的存储元件的第一电流; 并且引起从电力线到第一地址线的存储元件的第二电流。

公开(公告)号：US07915662B2

公开(公告)日：2011-03-29

申请号：US10918335

申请日：2004-08-13

申请人： Ronald Kakoschke ,  Thomas Nirschl ,  Danny Shum ,  Klaus Schrüfer

发明人： Ronald Kakoschke ,  Thomas Nirschl ,  Danny Shum ,  Klaus Schrüfer

IPC分类号： H01L29/788

摘要： A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.