Programmable logic device with cascading DSP slices
    61.
    发明授权
    Programmable logic device with cascading DSP slices 有权
    具有级联DSP片的可编程逻辑器件

    公开(公告)号:US07472155B2

    公开(公告)日:2008-12-30

    申请号:US11019783

    申请日:2004-12-21

    IPC分类号: G06F7/38

    摘要: Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.

    摘要翻译: 描述了可编程逻辑器件(PLD),其具有可以级联的DSP片段,以创建不同大小和复杂度的DSP电路。 每个DSP片包括多个操作数输入端口和片输出端口,所有这些端口都可编程地连接到通用路由和逻辑资源。 操作数端口接收处理的操作数,切片输出端口传送处理结果。 每个切片还包括连接到相应切片输出端口的反馈端口,以支持在该实施例中的累积功能,以及连接到上游切片的输出端口以支持级联的级联输入端口。

    Programmable logic device with pipelined DSP slices
    62.
    发明授权
    Programmable logic device with pipelined DSP slices 有权
    可编程逻辑器件,带流水线DSP片

    公开(公告)号:US07467175B2

    公开(公告)日:2008-12-16

    申请号:US11019782

    申请日:2004-12-21

    IPC分类号: G06F7/38

    CPC分类号: H03K19/17736 H03K19/17732

    摘要: Described is a programmable logic device (PLD) with columns of DSP slices that can be combined to create DSP circuits of varying size and complexity. DSP slices in accordance with some embodiments includes programmable operand input registers that can be configured to introduce different amounts of delay, from zero to two clock cycles, for example, to support pipelining. In one such embodiment, each DSP slice includes a partial-product generator having a multiplier port, a multiplicand port, and a product port. The multiplier and multiplicand ports connect to the operand input port via respective first and second operand input registers, each of which is capable of introducing from zero to two clock cycles of delay. In another embodiment, the output of at least one operand input register can connect to the input of an operand input register of a downstream DSP slice so that operands can be transferred among one or more slices.

    摘要翻译: 描述了可编程逻辑器件(PLD),其具有可以组合的DSP片段,以创建不同大小和复杂度的DSP电路。 根据一些实施例的DSP片段包括可被配置为从零到两个时钟周期引入不同量的延迟的可编程操作数输入寄存器,例如以支持流水线化。 在一个这样的实施例中,每个DSP片包括具有乘法器端口,被乘数端口和产品端口的部分乘积生成器。 乘法器和被乘数端口通过相应的第一和第二操作数输入寄存器连接到操作数输入端口,每个第一和第二操作数输入寄存器能够从零延迟到两个延迟的时钟周期。 在另一个实施例中,至少一个操作数输入寄存器的输出可以连接到下游DSP片的操作数输入寄存器的输入,使得操作数可以在一个或多个片之间传送。

    Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks
    63.
    发明授权
    Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks 有权
    在逻辑块阵列中提供紧密耦合的处理器和RAM块列的结构和方法

    公开(公告)号:US07181718B1

    公开(公告)日:2007-02-20

    申请号:US10928599

    申请日:2004-08-27

    IPC分类号: G06F17/50

    摘要: Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.

    摘要翻译: 在现有PLD架构中包含处理器能力的结构和方法,对现有的一般互连结构的影响最小。 在包括块RAM(BRAM)块的PLD中,BRAM块被修改以创建专用逻辑块,包括RAM,处理器和耦合在RAM,处理器和一般互连结构之间的专用接口 PLD。 通过增加BRAM块的列的宽度来获得附加区域。 因为互连结构几乎保持不变,所以专用逻辑块和相邻的瓦片之间的互连已经就位,并且修改不影响PLD路由软件。 在一些实施例中,处理器可以可选地被禁用,对于用户变得透明。 其他实施例提供了修改PLD以包括结构并提供上述能力的方法。

    Digital signal processing circuit having input register blocks
    64.
    发明申请
    Digital signal processing circuit having input register blocks 有权
    具有输入寄存器块的数字信号处理电路

    公开(公告)号:US20060230094A1

    公开(公告)日:2006-10-12

    申请号:US11432823

    申请日:2006-05-12

    IPC分类号: G06F7/52

    摘要: An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.

    摘要翻译: 一种集成电路,包括具有耦合到第一算术逻辑单元(ALU)电路的第一和第二寄存器块的数字信号处理元件(DSPE); 与顶部DSPE相邻的中间DSPE具有耦合到第二ALU电路的第三和第四寄存器块,其中第三寄存器块耦合到第一寄存器块,并且第四寄存器块寄存器块耦合到第二寄存器块 ; 以及与中间DSPE相邻的底部DSPE,具有耦合到第三ALU电路的第五和第六寄存器块,其中第五寄存器块耦合到第三寄存器块,并且第六寄存器块寄存器块耦合到第四寄存器块 。

    Encryption key for multi-key encryption in programmable logic device
    66.
    发明授权
    Encryption key for multi-key encryption in programmable logic device 有权
    可编程逻辑器件中多键加密的加密密钥

    公开(公告)号:US06957340B1

    公开(公告)日:2005-10-18

    申请号:US09724873

    申请日:2000-11-28

    IPC分类号: G06F21/00 H04L9/00 H04L9/14

    摘要: It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, an unencrypted bitstream could be observed and copied as it is being loaded. According to the invention, a bitstream for configuring a PLD with an encrypted design includes unencrypted words for controlling loading of the configuration bitstream and encrypted words that actually specify the design.

    摘要翻译: 有时期望保护PLD中使用的设计不被复制。 如果设计存储在与PLD不同的设备中并通过比特流读入PLD,则在加载时可以观察和复制未加密的比特流。 根据本发明,用于配置具有加密设计的PLD的比特流包括用于控制配置比特流的加载的未加密的字和实际指定设计的加密的字。

    Programmable logic device with cascading DSP slices
    67.
    发明申请
    Programmable logic device with cascading DSP slices 有权
    具有级联DSP片的可编程逻辑器件

    公开(公告)号:US20050144212A1

    公开(公告)日:2005-06-30

    申请号:US11019783

    申请日:2004-12-21

    摘要: Described is a programmable logic device (PLD) with columns of DSP slices that can be cascaded to create DSP circuits of varying size and complexity. Each DSP slice includes a plurality of operand input ports and a slice output port, all of which are programmably connected to general routing and logic resources. The operand ports receive operands for processing, and a slice output port conveys processed results. Each slice additionally includes a feedback port connected to the respective slice output port, to support accumulate functions in this embodiment, and a cascade input port connected to the output port of an upstream slice to support cascading.

    摘要翻译: 描述了可编程逻辑器件(PLD),其具有可以级联的DSP片段,以创建不同大小和复杂度的DSP电路。 每个DSP片包括多个操作数输入端口和片输出端口,所有这些端口都可编程地连接到通用路由和逻辑资源。 操作数端口接收处理的操作数,切片输出端口传送处理结果。 每个切片还包括连接到相应切片输出端口的反馈端口,以支持在该实施例中的累积功能,以及连接到上游切片的输出端口以支持级联的级联输入端口。

    Programmable logic device with hierarchical confiquration and state
storage
    70.
    发明授权
    Programmable logic device with hierarchical confiquration and state storage 失效
    具有分层配置和状态存储的可编程逻辑器件

    公开(公告)号:US5778439A

    公开(公告)日:1998-07-07

    申请号:US517019

    申请日:1995-08-18

    IPC分类号: H03K19/177 G06F12/02

    摘要: In accordance with the present invention, a programmable array includes hierarchical configuration and state storage. The array comprises an active storage for an active configuration and an active state as well as an inactive storage for one or more inactive configurations and one or more inactive states. The array further comprises logic and routing configured by the active configuration. The logic includes a plurality of combinational elements and a plurality of sequential logic elements for providing the states. Bits are transferred between the active and the inactive storage. The inactive storage is accessible for read or write operations by the active configuration by a structure comprising: a core including a plurality of configurable elements selectively coupled to each other, a memory controller for controlling the memory that configures the logic and routing in accordance with the active configuration, a command register to hold commands for the memory controller, a memory address register to address the memory, and a memory data register coupled to the memory and the plurality of combinational elements. In one embodiment, the array of the present invention includes a configurable routing structure for providing the active configuration access to the memory address register, the memory data register, and the command register. The configurable routing structure is generally controlled by signals from the user logic, thereby significantly increasing user flexibility in using the programmable array.

    摘要翻译: 根据本发明,可编程阵列包括分层配置和状态存储。 阵列包括用于活动配置和活动状态的活动存储器以及用于一个或多个非活动配置和一个或多个非活动状态的非活动存储器。 该阵列还包括由活动配置配置的逻辑和路由。 逻辑包括多个组合元件和用于提供状态的多个顺序逻辑元件。 位在活动和非活动存储之间传输。 非活动存储器可由活动配置通过以下结构进行读取或写入操作:包括:选择性地彼此耦合的多个可配置元件的核心;存储器控制器,用于根据所述存储器控制配置逻辑和路由 活动配置,用于保存用于存储器控制器的命令的命令寄存器,用于寻址存储器的存储器地址寄存器以及耦合到存储器和多个组合元件的存储器数据寄存器。 在一个实施例中,本发明的阵列包括用于提供对存储器地址寄存器,存储器数据寄存器和命令寄存器的有效配置访问的可配置路由结构。 可配置路由结构通常由来自用户逻辑的信号控制,从而显着增加用户使用可编程阵列的灵活性。