公开(公告)号：US06211027B1

公开(公告)日：2001-04-03

申请号：US09444278

申请日：1999-11-19

Applicant: Tony Lin ,  C. C. Hsue

Inventor： Tony Lin ,  C. C. Hsue

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/266 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659

Abstract: A method for manufacturing a PMOS transistor. A gate terminal is formed over a substrate. Spacers are formed on the sidewalls of the gate terminal. A source/drain terminal is formed in the substrate on each side of the gate terminal, and then a metal silicide layer is formed over the top surface of the gate terminal and the substrate. The spacers are next removed. Using the metal silicide layer as a mask, a source/drain extension region is formed in the substrate between the gate terminal and the source/drain terminal. Similarly, using the metal silicide layer as a mask, an anti-punchthrough region is form in the substrate interior under the source/drain extension region.

Abstract translation: 一种用于制造PMOS晶体管的方法。 栅极端子形成在基板上。 隔板形成在栅极端子的侧壁上。 源极/漏极端子形成在栅极端子的每一侧上的衬底中，然后在栅极端子和衬底的顶表面上形成金属硅化物层。 接下来移除间隔物。 使用金属硅化物层作为掩模，在栅极端子和源极/漏极端子之间的衬底中形成源极/漏极延伸区域。 类似地，使用金属硅化物层作为掩模，在源极/漏极延伸区域下方的衬底内部形成抗穿透区域。

公开(公告)号：US06187644B1

公开(公告)日：2001-02-13

申请号：US09391934

申请日：1999-09-08

Applicant: Tony Lin ,  Tung-Po Chen

Inventor： Tony Lin ,  Tung-Po Chen

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/28123 ,  H01L29/66545 ,  Y10S438/952

Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate, followed by forming a gate oxide layer and a conductive layer over the substrate. An anti-reflective coating is then formed on the conductive layer. After patterning to etch the anti-reflective coating and the conductive layer, a gate region is thus formed. A dielectric layer is formed over the gate region, and is then subjected to etching back, therefore forming an offset spacer on sidewall of the gate region while simultaneously removing surface oxide of the anti-reflective coating. Finally, anti-reflective coating is removed.

Abstract translation: 公开了一种用于形成半导体器件的方法。 该方法包括提供半导体衬底，随后在衬底上形成栅极氧化物层和导电层。 然后在导电层上形成抗反射涂层。 在图案化以蚀刻抗反射涂层和导电层之后，因此形成栅极区域。 在栅极区域上形成电介质层，然后对其进行蚀刻，从而在栅极区域的侧壁上形成偏移间隔物，同时去除抗反射涂层的表面氧化物。 最后，去除抗反射涂层。

公开(公告)号：USD434464S

公开(公告)日：2000-11-28

申请号：US108592

申请日：1999-08-02

Applicant: Tony Lin

Designer： Tony Lin

公开(公告)号：US6100191A

公开(公告)日：2000-08-08

申请号：US59687

申请日：1998-04-14

Applicant: Tony Lin ,  Water Lur ,  Jiun-Yuan Wu ,  Hsiao-Lin Lu

Inventor： Tony Lin ,  Water Lur ,  Jiun-Yuan Wu ,  Hsiao-Lin Lu

IPC: H01L21/285 ,  H01L21/44

CPC classification number: H01L21/28518 ,  H01L21/2855

Abstract: The present invention discloses a method to manufacture a self-aligned silicide layer on a substrate. A metal oxide semiconductor (MOS) device and a shallow trench are fabricated in the substrate. The device has a gate structure, spacers of the gate structured and doping regions. The shallow trench is refilled with silicon oxide material for isolation. A silicon layer is nonconformally deposited on the top surface of the gate structure, the spacers and the doping regions by using a physical vapor deposition (PVD) process, such as ion metal plasma (IMP) process. The IMP process, like a sputtering process, is to ionize a silicon material or a refractory-metal material to silicon ions or metal ions and the ions are biased to anisotropically deposit on the top surface of the substrate. A refractory metal layer is defined on the top surface of the silicon layer by the IMP technology. A two-step thermal annealing process, such as rapid thermal annealing (RTA) process is performed to convert the silicon layer and the refractory metal layer into a silicide layer. Since the silicon layer serves as a silicon source for the salicide process, the silicide layer can form on the spacers and the silicon oxide material of the trench.

Abstract translation: 本发明公开了一种在衬底上制造自对准硅化物层的方法。 在衬底中制造金属氧化物半导体（MOS）器件和浅沟槽。 器件具有栅极结构，栅极结构和掺杂区域的间隔物。 浅沟槽用氧化硅材料再填充以进行隔离。 通过使用诸如离子金属等离子体（IMP）工艺的物理气相沉积（PVD）工艺，硅层不均匀地沉积在栅极结构，间隔物和掺杂区域的顶表面上。 IMP工艺，如溅射工艺，是将硅材料或难熔金属材料离子化成硅离子或金属离子，并将离子偏置成各向异性沉积在衬底的顶表面上。 难熔金属层通过IMP技术限定在硅层的顶表面上。 进行两步热退火处理，例如快速热退火（RTA）工艺，以将硅层和难熔金属层转化为硅化物层。 由于硅层用作自对准硅化物工艺的硅源，硅化物层可以形成在间隔物和沟槽的氧化硅材料上。

公开(公告)号：US6048771A

公开(公告)日：2000-04-11

申请号：US85207

申请日：1998-05-27

Applicant: Tony Lin ,  Wen-Kuan Yeh ,  Juan-Yuan Wu

Inventor： Tony Lin ,  Wen-Kuan Yeh ,  Juan-Yuan Wu

IPC: H01L21/762 ,  H01L21/336 ,  H01L21/461 ,  H01L21/76

CPC classification number: H01L21/76229

Abstract: A method of forming a shallow trench isolation structure includes etching a substrate to form a trench. Then, an oxide layer is deposited in the trench and over the substrate by using high-density plasma. The oxide layer is pointed since it is formed by high-density plasma chemical vapor deposition. A stop layer made of silicon nitride, silicon oxy-nitride or boron nitride is formed on the oxide layer. The hardness of the stop layer is higher than that of the oxide layer so the protuberance of the oxide layer will be first removed during chemical mechanical polishing.

Abstract translation: 形成浅沟槽隔离结构的方法包括蚀刻衬底以形成沟槽。 然后，通过使用高密度等离子体，在沟槽和衬底上沉积氧化物层。 氧化层是尖锐的，因为它是通过高密度等离子体化学气相沉积形成的。 在氧化物层上形成由氮化硅，氮氧化硅或氮化硼制成的阻挡层。 停止层的硬度高于氧化物层的硬度，因此在化学机械抛光期间首先除去氧化物层的突起。

公开(公告)号：US06025274A

公开(公告)日：2000-02-15

申请号：US227950

申请日：1999-01-11

Applicant: Tony Lin ,  Jih-Wen Chou

Inventor： Tony Lin ,  Jih-Wen Chou

IPC: H01L21/336 ,  H01L21/00

CPC classification number: H01L29/6659 ,  H01L29/665

Abstract: A method fabricating salicide. A substrate having a polysilicon gate and a source/drain region is provided. A silicon oxide layer is formed on the polysilicon gate and the substrate. Using dry etch, a part of the silicon oxide layer is removed to leave a spacer with a waistline on a side wall of the polysilicon gate. A metal layer is formed on the polysilicon gate and the source/drain region. A rapid thermal process is performed to form a metal silicide

Abstract translation: 制造自杀剂的方法。 提供具有多晶硅栅极和源极/漏极区域的衬底。 在多晶硅栅极和衬底上形成氧化硅层。 使用干蚀刻，去除氧化硅层的一部分以在多晶硅栅极的侧壁上留下具有腰围的间隔物。 在多晶硅栅极和源极/漏极区域上形成金属层。 进行快速热处理以形成金属硅化物

公开(公告)号：US06008118A

公开(公告)日：1999-12-28

申请号：US59310

申请日：1998-04-13

Applicant: Wen-Kuan Yeh ,  Tony Lin ,  Heng-Sheng Huang

Inventor： Wen-Kuan Yeh ,  Tony Lin ,  Heng-Sheng Huang

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76849 ,  H01L21/76867

Abstract: A method of forming a barrier layer is disclosed. The barrier layer is formed on the upper surface of the tungsten plug. The method of forming the barrier layer is mainly a nitridation reaction. The nitridation reaction makes use of NH.sub.3 plasma, N.sub.2 plasma and N.sup.+ implantation.

Abstract translation: 公开了形成阻挡层的方法。 阻挡层形成在钨丝塞的上表面上。 形成阻挡层的方法主要是氮化反应。 氮化反应使用NH3等离子体，N2等离子体和N +注入。

公开(公告)号：US5981383A

公开(公告)日：1999-11-09

申请号：US814376

申请日：1997-03-11

Applicant: Water Lur ,  Tony Lin

Inventor： Water Lur ,  Tony Lin

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/423 ,  H01L21/70

CPC classification number: H01L29/6659 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L21/3205 ,  H01L21/32053 ,  H01L29/665 ,  H01L29/42376

Abstract: Salicide (self-aligned silicide) structures are formed using a process that does not form oxide spacer structures alongside polysilicon gate electrodes and wiring lines. A shaped polysilicon electrode is formed having protrusions extending beyond the sidewalls of the electrode. LDD source/drain regions are formed by ion implantation using only the polysilicon gate electrode as a mask, thereby forming LDD source drain/regions without using spacer oxide regions. Physical vapor deposition is used to deposit a metal layer having discontinuities at or adjacent the protrusions. A first rapid thermal anneal is performed to cause the metal to form a metal silicide over the polysilicon electrode. Unreacted metal is etched and then a second rapid thermal anneal is performed to convert the metal silicide to its lowest resistivity phase. Gate electrodes and wiring lines having this structure generally are formed having lower stress in the silicide layers, producing salicide structures having lower resistance than gate electrodes and wiring lines formed using conventional salicide techniques.

Abstract translation: 使用不与多晶硅栅电极和布线一起形成氧化物间隔结构的工艺来形成硅化物（自对准硅化物）结构。 形成具有延伸超过电极侧壁的突起的成形多晶硅电极。 通过仅使用多晶硅栅极作为掩模的离子注入形成LDD源极/漏极区域，从而在不使用间隔氧化物区域的情况下形成LDD源极漏极/区域。 物理气相沉积用于沉积在突起处或邻近突起处具有不连续性的金属层。 进行第一快速热退火以使金属在多晶硅电极上形成金属硅化物。 蚀刻未反应的金属，然后进行第二次快速热退火，以将金属硅化物转化为最低电阻率相。 具有这种结构的栅极电极和布线通常形成为在硅化物层中具有较低的应力，产生具有比栅电极低的电阻和使用常规自对准硅化物技术形成的布线的硅化物结构。

公开(公告)号：US5913124A

公开(公告)日：1999-06-15

申请号：US883332

申请日：1997-06-26

Applicant: Tony Lin ,  Water Lur

Inventor： Tony Lin ,  Water Lur

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/6659 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/665 ,  H01L21/26586

Abstract: A method of making a self-aligned silicide which has an impurity diffusion region in a lower part of the source/drain regions adjacent to the isolating region. The method includes performing an ion implantation operation at a large tilt angle, which increases the junction depth of the source/drain regions and prevents the metallic silicide lying at the edge of the isolating region from getting too close to the source/drain junction and causing unwanted current leakages. The isolating regions are overetched, which exposes the surface of the source/drain regions. The metal silicide layer can thus be formed over the exposed source/drain surfaces, resulting in more surface area for the formation of a wide border contact window, resulting in a lowering of both contact resistance and sheet resistance there.

Abstract translation: 一种制造自对准硅化物的方法，该硅化物在与隔离区相邻的源/漏区的下部具有杂质扩散区。 该方法包括以大的倾斜角执行离子注入操作，这增加了源极/漏极区的结深度，并且防止位于隔离区边缘处的金属硅化物太靠近源极/漏极结并导致 不必要的电流泄漏。 隔离区域被过蚀刻，其暴露源极/漏极区域的表面。 因此，可以在暴露的源极/漏极表面上形成金属硅化物层，导致形成宽边界接触窗的更多的表面积，从而导致接触电阻和薄层电阻的降低。

公开(公告)号：USD579359S1

公开(公告)日：2008-10-28

申请号：US29280939

申请日：2007-06-11

Applicant: James M. Critelli ,  Peter Lin ,  Tony Lin

Designer： James M. Critelli ,  Peter Lin ,  Tony Lin