公开(公告)号：US08697561B2

公开(公告)日：2014-04-15

申请号：US13372058

申请日：2012-02-13

申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/00

CPC分类号： H01L29/7851 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78645

摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.

摘要翻译： finFET结构包括位于衬底上的半导体鳍片。 栅电极穿过半导体鳍片。 栅电极具有邻接其侧壁的间隔层。 间隔层不完全覆盖半导体鳍片的侧壁。 栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上而不是衬底的相邻表面上，使得间隔层不完全覆盖 半导体鳍片 可以使用侧向生长方法制造其它微电子结构。

公开(公告)号：US07816743B2

公开(公告)日：2010-10-19

申请号：US12273894

申请日：2008-11-19

申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L29/06

CPC分类号： H01L29/7851 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78645

摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.

摘要翻译： finFET结构包括位于衬底上的半导体鳍片。 栅电极穿过半导体鳍片。 栅电极具有邻接其侧壁的间隔层。 间隔层不完全覆盖半导体鳍片的侧壁。 栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上而不是衬底的相邻表面上，使得间隔层不完全覆盖 半导体鳍片 可以使用侧向生长方法制造其它微电子结构。

公开(公告)号：US07659171B2

公开(公告)日：2010-02-09

申请号：US11850172

申请日：2007-09-05

申请人： Toshiharu Furukawa ,  Steven J Holmes ,  David V Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Steven J Holmes ,  David V Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/76829 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for forming a borderless contact for a semiconductor FET (Field Effect Transistor) device, the method comprising, forming a gate conductor stack on a substrate, forming spacers on the substrate, such that the spacers and the gate conductor stack partially define a volume above the gate conductor stack, wherein the spacers are sized to define the volume such that a stress liner layer deposited on the gate conductor stack substantially fills the volume, depositing a liner layer on the substrate, the spacers, and the gate conductor stack, depositing a dielectric layer on the liner layer, etching to form a contact hole in the dielectric layer, etching to form the contact hole in the liner layer, such that a portion of a source/drain diffusion area formed in the substrate is exposed and depositing contact metal in the contact hole.

摘要翻译： 一种用于形成半导体FET（场效应晶体管）器件的无边界接触的方法，所述方法包括：在衬底上形成栅极导体堆叠，在衬底上形成间隔物，使得间隔物和栅极导体堆叠部分地限定体积 在栅极导体堆叠之上，其中间隔物的尺寸设定成限定体积，使得沉积在栅极导体堆叠上的应力衬垫层基本上填充体积，在衬底，间隔物和栅极导体堆叠上沉积衬垫层，沉积 衬底层上的电介质层，蚀刻以在电介质层中形成接触孔，蚀刻以在衬垫层中形成接触孔，使得在衬底中形成的源极/漏极扩散区域的一部分被暴露并沉积接触 接触孔中的金属。

公开(公告)号：US20090075439A1

公开(公告)日：2009-03-19

申请号：US12273908

申请日：2008-11-19

申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/336

CPC分类号： H01L29/7851 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78645

摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.

摘要翻译： finFET结构包括位于衬底上的半导体鳍片。 栅电极穿过半导体鳍片。 栅电极具有邻接其侧壁的间隔层。 间隔层不完全覆盖半导体鳍片的侧壁。 栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上，而不是在衬底的邻接表面上，使得间隔层不完全覆盖半导体的侧壁 鳍。 可以使用侧向生长方法制造其它微电子结构。

公开(公告)号：US20120142182A1

公开(公告)日：2012-06-07

申请号：US13372058

申请日：2012-02-13

申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/28

CPC分类号： H01L29/7851 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/78645

摘要： A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate, so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.

摘要翻译： finFET结构包括位于衬底上的半导体鳍片。 栅电极穿过半导体鳍片。 栅电极具有邻接其侧壁的间隔层。 间隔层不完全覆盖半导体鳍片的侧壁。 栅电极和间隔层可以使用气相沉积法形成，该方法提供选择性沉积在心轴层的侧壁上而不是在基底的相邻表面上，使得间隔层不完全覆盖 半导体鳍片 可以使用侧向生长方法制造其它微电子结构。

公开(公告)号：US07084060B1

公开(公告)日：2006-08-01

申请号：US10908244

申请日：2005-05-04

申请人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

发明人： Toshiharu Furukawa ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III

IPC分类号： H01L21/44

CPC分类号： H01L21/76876 ,  B82Y30/00 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76867 ,  Y10S438/902

摘要： Methods of forming a capping layer over a metal wire structure of a semiconductor device are disclosed. In one embodiment, the method includes providing a partially fabricated semiconductor device having exposed surfaces of the metal (e.g., copper) wire structure and a dielectric around the metal wire structure. The exposed surface of the metal wire structure is then activated by forming a seed layer thereon. The capping layer is then formed over the exposed surface of the metal wire structure by performing a selective atomic layer deposition (ALD) of a capping layer material onto the metal wire structure. As an alternative, the dielectric may be masked off to further assist the selectivity of the ALD. The invention also includes a semiconductor structure including the metal wire structure having an atomic layer deposition capping layer over an upper surface thereof.

摘要翻译： 公开了在半导体器件的金属线结构上形成覆盖层的方法。 在一个实施例中，该方法包括提供部分制造的半导体器件，其具有金属（例如铜）线结构的暴露表面和金属线结构周围的电介质。 然后通过在其上形成种子层来激活金属线结构的暴露表面。 然后通过在金属线结构上执行覆盖层材料的选择性原子层沉积（ALD），在金属线结构的暴露表面上形成覆盖层。 作为替代方案，可以掩蔽电介质以进一步有助于ALD的选择性。 本发明还包括一种半导体结构，其包括在其上表面上具有原子层沉积覆盖层的金属线结构。

公开(公告)号：US07026259B2

公开(公告)日：2006-04-11

申请号：US10707894

申请日：2004-01-21

申请人： Mark C. Hakey ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell

发明人： Mark C. Hakey ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell

IPC分类号： H01L21/26 ,  G06F17/50 ,  G03B27/42

CPC分类号： G03F7/70341 ,  Y10S438/947

摘要： A liquid-filled balloon may be positioned between a workpiece, such as a semiconductor structure covered with a photoresist, and a lithography light source. The balloon includes a thin membrane that exhibits good optical and physical properties. Liquid contained in the balloon also exhibits good optical properties, including a refractive index higher than that of air. Light from the lithography light source passes through a mask, through a top layer of the balloon membrane, through the contained liquid, through a bottom layer of the balloon membrane, and onto the workpiece where it alters portions of the photoresist. As the liquid has a low absorption and a higher refractive index than air, the liquid-filled balloon system enhances resolution. Thus, the balloon provides optical benefits of liquid immersion without the complications of maintaining a liquid between (and in contact with) a lithographic light source mechanism and workpiece.

摘要翻译： 液体填充的球囊可以位于诸如被光致抗蚀剂覆盖的半导体结构的工件和光刻光源之间。 气球包括显示出良好的光学和物理性质的薄膜。 包含在气囊中的液体也表现出良好的光学性能，包括折射率高于空气的折射率。 来自光刻光源的光通过球囊膜的顶层通过所包含的液体通过球囊膜的底层，并穿过其上改变部分光致抗蚀剂的工件。 由于液体具有比空气低的吸收和较高的折射率，所以充满液体的球囊系统提高了分辨率。 因此，气囊提供液体浸没的光学优点，而没有在平版印刷光源机构和工件之间（并与之接触）之间保持液体的并发症。

公开(公告)号：US08946866B2

公开(公告)日：2015-02-03

申请号：US13490239

申请日：2012-06-06

申请人： Charles W. Koburger, III ,  Steven J. Holmes ,  David V. Horak ,  Kurt R. Kimmel ,  Karen E. Petrillo ,  Christopher F. Robinson

发明人： Charles W. Koburger, III ,  Steven J. Holmes ,  David V. Horak ,  Kurt R. Kimmel ,  Karen E. Petrillo ,  Christopher F. Robinson

IPC分类号： H01L29/06 ,  G03F7/20

CPC分类号： G03F7/70691 ,  G03F7/70341 ,  G03F7/70808

摘要： An article including a microelectronic substrate is provided as an article usable during the processing of the microelectronic substrate. Such article includes a microelectronic substrate having a front surface, a rear surface opposite the front surface and a peripheral edge at boundaries of the front and rear surfaces. The front surface is a major surface of the article. A removable annular edge extension element having a front surface, a rear surface and an inner edge extending between the front and rear surfaces has the inner edge joined to the peripheral edge of the microelectronic substrate. In such way, a continuous surface is formed which includes the front surface of the edge extension element extending laterally from the peripheral edge of the microelectronic substrate and the front surface of the microelectronic substrate, the continuous surface being substantially co-planar and flat where the peripheral edge is joined to the inner edge.

摘要翻译： 提供包括微电子衬底的制品作为在微电子衬底的处理期间可用的制品。 这种物品包括具有前表面，与前表面相对的后表面和在前表面和后表面的边界处的周边边缘的微电子基底。 前表面是物品的主要表面。 具有前表面，后表面和在前表面和后表面之间延伸的内边缘的可拆卸的环形边缘延伸元件具有接合到微电子基板的周边边缘的内边缘。 以这种方式，形成连续表面，其包括边缘延伸元件的前表面，该边缘延伸元件从微电子基底的周边边缘和微电子基底的前表面横向延伸，连续表面基本上共平面且平坦， 周缘连接到内边缘。

公开(公告)号：US20140061930A1

公开(公告)日：2014-03-06

申请号：US13604660

申请日：2012-09-06

申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.

摘要翻译： 提供了一种方法，其包括首先根据第一掩模蚀刻衬底。 第一蚀刻在衬底中形成第一深度的第一蚀刻特征。 第一蚀刻还在衬底中形成条条开口。 然后可以用填充材料填充条子开口。 可以通过去除第一掩模的一部分来形成第二掩模。 可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。 第二蚀刻将第一蚀刻特征延伸到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。 然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。

公开(公告)号：US20130328208A1

公开(公告)日：2013-12-12

申请号：US13490542

申请日：2012-06-07

申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L21/76897 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

摘要翻译： 在第一介电材料层的线沟槽内形成第一金属线和第一介电帽材料部分的堆叠。 之后形成第二电介质材料层。 在第二介电材料层的顶表面和底表面之间延伸的线沟槽被图案化。 将光致抗蚀剂层施加在第二介电材料层上并用通孔图案构图。 通过对第一和第二介电材料层的介电材料的选择性蚀刻来去除第一电介质盖材料的下部，以形成沿着线沟槽的宽度方向横向限制并沿着宽度方向的 第一条金属线。 形成双镶嵌线和通孔结构，其包括沿着两个独立的水平方向横向限制的通孔结构。