公开(公告)号：US08115327B2

公开(公告)日：2012-02-14

申请号：US12447085

申请日：2007-08-30

Applicant: Tomonari Yomoda ,  Toshio Yoshida

Inventor： Tomonari Yomoda ,  Toshio Yoshida

IPC: F03B13/00

CPC classification number: H02J7/32 ,  H04M1/021 ,  H04M1/21 ,  Y02B40/90

Abstract: There is provided a portable electronic device capable of being immediately operated without the use of a battery even when the battery reaches exhaustion. An electricity generating unit 131 is embedded in the portable electronic device. The electricity generating unit 131 has a mechanism to pull out a pull line 113 wound around a pulley 135 to wind up a spiral spring 133 and a mechanism to transfer torque occurring when the spiral spring 133 is released and to rotate the motor at high speed. An output voltage from the motor 142 is adjusted and smoothed by a constant voltage circuit and is directly supplied as power to power consuming components. The portable electronic device connecting two flips can wind up the spiral spring 133 by opening and closing the two flips.

Abstract translation: 提供了即使在电池耗尽时也能立即使用电池而不使用电池的便携式电子设备。 发电单元131嵌入在便携式电子设备中。 发电单元131具有拉出缠绕在滑轮135上的拉线113以卷起螺旋弹簧133的机构，以及用于传递当螺旋弹簧133被释放时发生的扭矩并且使马达高速旋转的机构。 来自电动机142的输出电压由恒定电压电路调节和平滑，并且直接作为功率供应给功率消耗部件。 连接两个翻转件的便携式电子设备可以通过打开和关闭两个翻转来卷起螺旋弹簧133。

公开(公告)号：US08019973B2

公开(公告)日：2011-09-13

申请号：US12638764

申请日：2009-12-15

Applicant: Takashi Suzuki ,  Toshio Yoshida

Inventor： Takashi Suzuki ,  Toshio Yoshida

IPC: G06F9/312 ,  G06F9/52

CPC classification number: G06F9/3885 ,  G06F9/30127 ,  G06F9/3824 ,  G06F9/3851

Abstract: An information processing apparatus and a method of controlling the same that employs a register window system and a Simultaneous Multithreading method for reducing circuit areas by sharing a data transfer bus between threads, said bus connecting a master register and a work register provided for each thread and for avoiding interference in instruction execution with other threads caused by a conflict between accesses to a register between threads. An information processing apparatus and a method of controlling the information processing apparatus employing a register window system for register reading, in which a master register and a work register are held for each thread and a bus for transferring data from the master to the work register is shared by threads in order to realize Simultaneous Multithreading.

Abstract translation: 一种信息处理装置及其控制方法，其采用寄存器窗口系统和同时多线程方法，用于通过在线程之间共享数据传输总线来减少电路面积，所述总线连接主寄存器和为每个线程提供的工作寄存器， 用于避免在对线程之间的寄存器的访问之间的冲突引起的与其他线程的指令执行的干扰。 一种信息处理设备和方法，用于控制信息处理设备，该信息处理设备采用用于寄存器读取的寄存器窗口系统，其中为每个线程保持主寄存器和工作寄存器，并且用于将数据从主器件传送到工作寄存器的总线是 由线程共享，以实现同时多线程。

公开(公告)号：US07958338B2

公开(公告)日：2011-06-07

申请号：US12591993

申请日：2009-12-07

Applicant: Yasunobu Akizuki ,  Toshio Yoshida ,  Tomohiro Tanaka ,  Ryuji Kan

Inventor： Yasunobu Akizuki ,  Toshio Yoshida ,  Tomohiro Tanaka ,  Ryuji Kan

IPC: G06F9/38 ,  G06F9/52

CPC classification number: G06F9/3851 ,  G06F9/30123 ,  G06F9/30127 ,  G06F9/30141

Abstract: An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (22-0, 22-1) for each thread, and a selection circuit (32, 24) which, when an operand data required for executing a function is read from a register file (20), selects in advance a thread to be read from the register file (20). This makes it possible to select an architecture register at an early stage, and although the number of circuits in a portion for selecting the architecture registers increases, the wiring amount of the circuits can be decreased, because the architecture register of the thread to be read is selected in advance.

Abstract translation: 指令执行控制装置在同时多线程系统中操作多个线程。 该装置具有针对每个线程的架构寄存器（22-0,22-1）和选择电路（32,24），当从寄存器文件（20）读取执行功能所需的操作数数据时，选择 推进从注册文件（20）读取的线程。 这使得能够在早期阶段选择体系结构寄存器，并且尽管用于选择架构寄存器的部分中的电路数量增加，但是由于要读取的线程的体系结构寄存器可以减少电路的布线量 提前选择。

公开(公告)号：US20100100709A1

公开(公告)日：2010-04-22

申请号：US12654262

申请日：2009-12-15

Applicant: Toshio Yoshida

Inventor： Toshio Yoshida

IPC: G06F9/312 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/3802 ,  G06F9/3857 ,  G06F9/3859

Abstract: In a CPU having a SMT function of executing plural threads composed of a series of instructions representing processing, there are provided a decode section for decoding processing represented by instructions of plural threads, an instruction buffer for obtaining instructions from a thread and holding the instructions, and inputting the held instructions to the decode section in order in the thread, and an execution pipeline for executing processing of instructions decoded by the decode section. The decode section checks whether or not an executable condition is ready for an instruction when the instruction is decoded and requests that the instructions held in the instruction buffer and an instruction subsequent to an instruction that is not ready with an executable condition are inputted again to the decode section.

Abstract translation: 在具有执行由表示处理的一系列指令构成的多个线程的SMT功能的CPU中，提供了一种用于解码由多个线程的指令表示的处理的解码部分，用于从线程获取指令并保持指令的指令缓冲器， 以及在所述线程中按顺序将所保持的指令输入到所述解码部分，以及用于执行由所述解码部件解码的指令的处理的执行流水线。 解码部分在指令被解码时检查可执行条件是否准备好用于指令，并且请求将保持在指令缓冲器中的指令和未准备好可执行条件的指令之后的指令再次输入到 解码部分。

公开(公告)号：US20100095093A1

公开(公告)日：2010-04-15

申请号：US12638764

申请日：2009-12-15

Applicant: Takashi SUZUKI ,  Toshio Yoshida

Inventor： Takashi SUZUKI ,  Toshio Yoshida

IPC: G06F9/30

CPC classification number: G06F9/3885 ,  G06F9/30127 ,  G06F9/3824 ,  G06F9/3851

Abstract: An information processing apparatus and a method of controlling the same that employs a register window system and a Simultaneous Multithreading method for reducing circuit areas by sharing a data transfer bus between threads, said bus connecting a master register and a work register provided for each thread and for avoiding interference in instruction execution with other threads caused by a conflict between accesses to a register between threads. An information processing apparatus and a method of controlling the information processing apparatus employing a register window system for register reading, in which a master register and a work register are held for each thread and a bus for transferring data from the master to the work register is shared by threads in order to realize Simultaneous Multithreading.

Abstract translation: 一种信息处理装置及其控制方法，其采用寄存器窗口系统和同时多线程方法，用于通过在线程之间共享数据传输总线来减少电路面积，所述总线连接主寄存器和为每个线程提供的工作寄存器， 用于避免在对线程之间的寄存器的访问之间的冲突引起的与其他线程的指令执行的干扰。 一种信息处理设备和方法，用于控制信息处理设备，该信息处理设备采用用于寄存器读取的寄存器窗口系统，其中为每个线程保持主寄存器和工作寄存器，并且用于将数据从主器件传送到工作寄存器的总线是 由线程共享，以实现同时多线程。

公开(公告)号：US20100093568A1

公开(公告)日：2010-04-15

申请号：US12307375

申请日：2007-07-03

Applicant: Kazuo Tagawa ,  Yuji Shimomura ,  Ken Sawada ,  Katsuya Takigawa ,  Toshio Yoshida ,  Shinichi Mitsimoto ,  Eiji Akiyama ,  Junichi Shibata ,  Satoshi Suda ,  Hideo Yokota ,  Masahiro Hata ,  Hiroyuki Hoshino ,  Hajime Nakao ,  Shozaburo Konishi

Inventor： Kazuo Tagawa ,  Yuji Shimomura ,  Ken Sawada ,  Katsuya Takigawa ,  Toshio Yoshida ,  Shinichi Mitsimoto ,  Eiji Akiyama ,  Junichi Shibata ,  Satoshi Suda ,  Hideo Yokota ,  Masahiro Hata ,  Hiroyuki Hoshino ,  Hajime Nakao ,  Shozaburo Konishi

IPC: C10M159/04 ,  C10M169/00 ,  C10M129/54 ,  C10M129/04 ,  C10M133/12 ,  C10M129/26 ,  C10M143/02

CPC classification number: C10M171/008 ,  C10M101/02 ,  C10M107/02 ,  C10M169/04 ,  C10M2203/06 ,  C10M2203/065 ,  C10M2203/1006 ,  C10M2203/1025 ,  C10M2205/024 ,  C10M2205/0285 ,  C10M2205/173 ,  C10M2207/021 ,  C10M2207/026 ,  C10M2207/04 ,  C10M2207/042 ,  C10M2207/10 ,  C10M2207/126 ,  C10M2207/144 ,  C10M2207/24 ,  C10M2207/262 ,  C10M2207/28 ,  C10M2207/281 ,  C10M2207/289 ,  C10M2207/40 ,  C10M2209/084 ,  C10M2215/064 ,  C10M2215/065 ,  C10M2215/223 ,  C10M2219/024 ,  C10M2219/046 ,  C10M2219/066 ,  C10M2219/068 ,  C10M2219/082 ,  C10M2219/084 ,  C10M2219/085 ,  C10M2219/086 ,  C10M2219/106 ,  C10M2223/04 ,  C10M2223/041 ,  C10M2223/042 ,  C10M2223/043 ,  C10M2223/045 ,  C10M2223/047 ,  C10N2210/01 ,  C10N2210/02 ,  C10N2210/06 ,  C10N2220/022 ,  C10N2220/024 ,  C10N2220/025 ,  C10N2220/028 ,  C10N2220/031 ,  C10N2220/032 ,  C10N2220/302 ,  C10N2220/303 ,  C10N2220/306 ,  C10N2230/02 ,  C10N2230/04 ,  C10N2230/06 ,  C10N2230/08 ,  C10N2230/10 ,  C10N2230/30 ,  C10N2230/74 ,  C10N2230/76 ,  C10N2240/06 ,  C10N2240/08 ,  C10N2240/30 ,  C10N2240/401 ,  C10N2240/402 ,  C10N2240/409 ,  C10N2280/00 ,  C10M2205/022

Abstract: The present invention provides a refrigerating machine oil, a compressor oil composition, a hydraulic oil composition, a metalworking oil composition, a heat treating oil composition, a lubricating oil composition for machine tools and a lubricating oil composition which comprise a lubricating oil base oil having % CA of not more than 2, % CP/% CN of not less than 6 and an iodine value of not more than 2.5.

Abstract translation: 本发明提供一种制冷机油，压缩机油组合物，液压油组合物，金属加工油组合物，热处理油组合物，机床用润滑油组合物和润滑油组合物，其含有具有 ％CA不超过2，％CP /％CN不低于6，碘值不大于2.5。

公开(公告)号：US07590827B2

公开(公告)日：2009-09-15

申请号：US10347407

申请日：2003-01-21

Applicant: Toshio Yoshida

Inventor： Toshio Yoshida

IPC: G06F9/00

CPC classification number: G06F9/3842 ,  G06F9/384

Abstract: A latest register update buffer which stores latest register update data is allocated and prepared every general register for storing source data. A latest register update processing unit stores a value in the general register as latest register update data into the latest register update buffer when a register update instruction is not speculatively executed, and overwrites a result of the speculative execution when the instruction is speculatively executed. Upon instruction decoding, a matching processing unit reads out the latest register update data from the latest register update allocation buffer and stores it into a data area in a reservation station.

Abstract translation: 分配并准备存储最新的寄存器更新数据的最新的寄存器更新缓冲器，用于存储源数据的每个通用寄存器。 当不推测性地执行寄存器更新指令时，最新的寄存器更新处理单元将通用寄存器中的值作为最新的寄存器更新数据存储到最新的寄存器更新缓冲器中，并且当推测性地执行指令时，覆盖推测执行的结果。 在指令解码时，匹配处理单元从最新的寄存器更新分配缓冲器中读出最新的寄存器更新数据，并将其存储到保留站中的数据区中。

公开(公告)号：US20080228846A1

公开(公告)日：2008-09-18

申请号：US12047782

申请日：2008-03-13

Applicant: Mikio HONDOU ,  Ryuji Kan ,  Toshio Yoshida

Inventor： Mikio HONDOU ,  Ryuji Kan ,  Toshio Yoshida

IPC: G06F7/483

CPC classification number: G06F7/548 ,  G06F1/02 ,  G06F7/483 ,  G06F7/5443

Abstract: A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.

Abstract translation: 一种处理装置，包括存储操作数数据的寄存器，读取存储在寄存器中的操作数数据的寄存器数据读取部分，存储存储泰勒级数运算系数数据的系数表的系数表存储部分，读取 使用泰勒级数的度数信息和系数表识别信息的系数表组存储部分的泰勒级数系数数据和使用由系数数据读取部分读取的系数数据执行泰勒级数操作的浮点乘法器 ，从寄存器读取的数据。

公开(公告)号：US07343478B2

公开(公告)日：2008-03-11

申请号：US11333229

申请日：2006-01-18

Applicant: Ryuji Kan ,  Hideo Yamashita ,  Toshio Yoshida

Inventor： Ryuji Kan ,  Hideo Yamashita ,  Toshio Yoshida

IPC: G06F9/44

CPC classification number: G06F9/30043 ,  G06F9/30127 ,  G06F9/3851

Abstract: The present apparatus reduces hardware resources and improves data read throughput in an information processing apparatus employing the out-of-order instruction execution method. The apparatus includes: an arithmetic operation unit which executes a window switching instruction and an instruction relating to data stored in the current register or data held in the replacing buffer; and a control unit which transfers, if a window switching instruction is decoded at execution of the window switching instruction by the arithmetic operation unit, data of the register window which is to be specified by the current window pointer upon completion of execution of the window switching instruction, to the replacing buffer.

Abstract translation: 本装置在采用无序指令执行方法的信息处理装置中减少硬件资源并提高数据读取吞吐量。 该装置包括：算术运算单元，执行窗口切换指令和与存储在当前寄存器中的数据或保存在替换缓冲器中的数据有关的指令; 以及控制单元，如果在由算术运算单元执行窗口切换指令时对窗口切换指令进行了解码，则在完成窗口切换的执行完成后由当前窗口指针指定的寄存器窗口的数据 指令，到替换缓冲区。

公开(公告)号：US07175348B2

公开(公告)日：2007-02-13

申请号：US11218552

申请日：2005-09-06

Applicant: Nobuaki Fujimura ,  Toshio Yoshida

Inventor： Nobuaki Fujimura ,  Toshio Yoshida

IPC: F16C29/06

CPC classification number: F16C29/0657

Abstract: A slider is formed by a metallic main body, a synthetic resin-made frame, and a pair of end caps. The frame is detachably fitted to outer sides of the main body. Ball rolling grooves are provided in the main body. Return paths and inside grooves of a direction changing path are provided in the frame. An outside groove of the direction changing path are provided in each end cap. A paste-like filler is applied to a boundary portion between the main body and the frame and a boundary portion between the frame and the end cap, and is allowed to cure.

Abstract translation: 滑块由金属主体，合成树脂制框架和一对端盖形成。 框架可拆卸地装配到主体的外侧。 滚珠槽设置在主体中。 返回路径和方向改变路径的内侧凹槽设置在框架中。 在每个端盖中设置有方向改变路径的外槽。 将糊状填料施加到主体和框架之间的边界部分以及框架和端盖之间的边界部分，并允许其固化。