公开(公告)号：US20180197865A1

公开(公告)日：2018-07-12

申请号：US15859756

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Tsen Liu ,  Li-Wei Feng ,  Chien-Ting Ho

IPC: H01L27/108 ,  H01L29/08 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L27/10808 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L29/0847

Abstract: A semiconductor device and a manufacturing method thereof are provided. The method includes providing a substrate, a plurality of word lines and a plurality of bit lines, and then forming a storage node contact on each source/drain region, so that a width of a top surface of each storage node contact in a direction is less than a width of a bottom surface of each storage node contact.

公开(公告)号：US20180190659A1

公开(公告)日：2018-07-05

申请号：US15856024

申请日：2017-12-27

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Chien-Ting Ho ,  Shih-Fang Tzou ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L27/10855 ,  H01L21/02071 ,  H01L21/28247 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894

Abstract: A manufacturing method of a semiconductor memory device is provided in the present invention. A cleaning treatment to a storage node contact on a semiconductor substrate is performed, and a metal silicide layer is formed after the cleaning treatment. A gate contact opening penetrating a capping layer of a transistor on the semiconductor substrate is formed after the step of forming the metal silicide layer for exposing a gate structure of the transistor. By the manufacturing method of the semiconductor memory device in the present invention, the gate structure of the transistor may be kept from being influenced and/or damaged by the cleaning treatment of the storage node contact, and the electrical performance of the transistor may be ensured accordingly.

公开(公告)号：US20180151666A1

公开(公告)日：2018-05-31

申请号：US15362771

申请日：2016-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tri-Rung Yew ,  Hung-Chan Lin ,  Li-Wei Feng ,  Chien-Ting Ho ,  Chia-Lung Chang

IPC: H01L49/02 ,  H01L21/311 ,  H01L21/3205 ,  H01L27/108

CPC classification number: H01L28/82 ,  H01L21/31111 ,  H01L21/32051 ,  H01L27/10852

Abstract: A method of fabricating a metal-insulator-metal capacitor includes providing a dielectric layer. The dielectric layer is etched to form a first hole including a first convex profile bulging into the dielectric layer. Subsequently, the dielectric layer is etched to form a second hole including a second convex profile bulging into the dielectric layer. A first metal layer is formed to conformally cover the capacitor trench. An insulating layer is formed to cover the first metal layer. Finally, a second metal layer is formed covering the insulating layer.