公开(公告)号：US09881831B2

公开(公告)日：2018-01-30

申请号：US15465606

申请日：2017-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yi Chiu ,  Shih-Fang Hong ,  Chao-Hung Lin

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure is disposed on the silicon substrate and includes a silicon germanium (SiGe) layer extending from bottom to top in the fin shaped structure. The shallow trench isolation covers a bottom portion of the fin shaped structure.

公开(公告)号：US20170345937A1

公开(公告)日：2017-11-30

申请号：US15678100

申请日：2017-08-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yi Chiu

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/06 ,  H01L21/321 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/32105 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/66795

Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate including a first semiconductor material is provided. The semiconductor substrate includes a dielectric structure formed thereon, and the dielectric structure includes at least a recess formed therein. A first epitaxial layer is then formed in the recess. The first epitaxial layer includes at least a second semiconductor material that a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. Subsequently, a thermal oxidation process is performed to the first epitaxial layer thereby forming a semiconductor layer at a bottom of the recess and a silicon oxide layer on the semiconductor layer. After removing the silicon oxide layer, a second epitaxial layer is formed on the semiconductor layer in the recess.

公开(公告)号：US20170047447A1

公开(公告)日：2017-02-16

申请号：US14855390

申请日：2015-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yi Chiu ,  Shih-Fang Hong ,  Chao-Hung Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/165 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure is disposed on the silicon substrate and includes a silicon germanium (SiGe) layer extending downwardly from a top end and at least occupying 80% to 90% of the fin shaped structure. The shallow trench isolation covers a bottom portion of the fin shaped structure.

Abstract translation: 半导体器件及其制造方法，半导体器件包括硅衬底，鳍状结构和浅沟槽隔离。 鳍状结构设置在硅衬底上，并且包括从顶端向下延伸并且至少占据鳍形结构的80％至90％的硅锗（SiGe）层。 浅沟槽隔离覆盖鳍状结构的底部。

公开(公告)号：US09385048B2

公开(公告)日：2016-07-05

申请号：US14018439

申请日：2013-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Hong ,  Chung-Yi Chiu

IPC: H01L21/027 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L21/823821 ,  H01L21/845 ,  H01L29/6681

Abstract: The present invention provides a method of forming Fin-FET. A substrate with an active region and a dummy region are defined thereon. A plurality of first fins and second fins are formed in the active region, and a plurality of dummy fins are formed in the dummy region and the active region. A first active region is provided in the active region. A revised first active region is formed by extending the first active region to cover at least one adjacent dummy fin. Next, a first dummy region is provided in the dummy region. A first mask layout is formed by combining the revised first active region and the first dummy region. A first patterned mask layer is formed by using the first mask layout. A first epitaxial process is performed for the first fins and the dummy fins exposed by the first patterned mask layer.