公开(公告)号：US11605631B2

公开(公告)日：2023-03-14

申请号：US17516721

申请日：2021-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Chen Chiu ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chien-Liang Wu ,  Chih-Kai Kang ,  Guan-Kai Huang

IPC: H01L27/085 ,  H01L27/06 ,  H01L29/66 ,  H01L29/778

Abstract: A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.

公开(公告)号：US20230071086A1

公开(公告)日：2023-03-09

申请号：US17987795

申请日：2022-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Hsiang Huang ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region and a first metal interconnection on the MTJ. Preferably, a top view of the MTJ includes a circle and a top view of the first metal interconnection includes an ellipse overlapping the circle.

公开(公告)号：US20220328504A1

公开(公告)日：2022-10-13

申请号：US17320234

申请日：2021-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai ,  Chih-Kai Kang

IPC: H01L27/112 ,  G11C17/16

Abstract: A bit cell structure for one-time programming is provided in the present invention, including a substrate, a first doped region in the substrate and electrically connecting a source line, a second doped region in the substrate and having a source and a drain electrically connecting a bit line, a heavily-doped channel in the substrate and connecting the first doped region and the source of second doped region, and a word line crossing over the second dope region between the source and the drain.

公开(公告)号：US20220328503A1

公开(公告)日：2022-10-13

申请号：US17314061

申请日：2021-05-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chang-Chien Wong ,  Sheng-Yuan Hsueh ,  Ching-Hsiang Tseng ,  Chi-Horn Pai ,  Shih-Chieh Hsu

IPC: H01L27/112

Abstract: A one-time programmable (OTP) memory cell includes a substrate comprising an active area surrounded by an isolation region, a transistor disposed on the active area, and a diffusion-contact fuse electrically coupled to the transistor. The diffusion-contact fuse includes a diffusion region in the active area, a silicide layer on the diffusion region, and a contact partially landed on the silicide layer and partially landed on the isolation region.

公开(公告)号：US20220181478A1

公开(公告)日：2022-06-09

申请号：US17676867

申请日：2022-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang ,  Guan-Kai Huang ,  Chien-Liang Wu

IPC: H01L29/778 ,  H01L29/66

Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

公开(公告)号：US11322215B1

公开(公告)日：2022-05-03

申请号：US17326375

申请日：2021-05-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Pin Tsao ,  Tsung-Hsun Wu ,  Liang-Wei Chiu ,  Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Kun-Hsien Lee ,  Chang-Chien Wong

IPC: G11C17/14 ,  G11C17/16 ,  G11C17/18

Abstract: A one-time programmable (OTP) memory device includes a first memory cell, which further includes a first source line extending along a first direction on a substrate, a first word line extending along the first direction on one side of the first source line, a second word line extending along the first direction on another side of the first source line, a first diffusion region extending along a second direction adjacent to two sides of the first word line and the second word line, and a first metal interconnection connecting the first word line and the second word line.

公开(公告)号：US11316031B2

公开(公告)日：2022-04-26

申请号：US16741725

申请日：2020-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Chih-Kai Kang

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L21/84

Abstract: A method of forming a fin forced stack inverter includes the following steps. A substrate including a first fin, a second fin and a third fin across a first active area along a first direction is provided, wherein the first fin, the second fin and the third fin are arranged side by side. A fin remove inside active process is performed to remove at least a part of the second fin in the first active area. A first gate is formed across the first fin and the third fin in the first active area along a second direction. The present invention also provides a 1-1 fin forced fin stack inverter formed by said method.

公开(公告)号：US20220059616A1

公开(公告)日：2022-02-24

申请号：US17074584

申请日：2020-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh

IPC: H01L27/24 ,  H01L43/12 ,  H01L27/22 ,  H01L45/00

Abstract: The invention discloses a memory fabrication method. The memory fabrication method includes forming a plurality of gate electrode lines to respectively form a plurality of gates of a plurality of data storage cells, and forming a plurality of conductive lines. The plurality of data storage cells are arranged in an array. Each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines. Each of the plurality of conductive lines at least partially overlaps the two gate electrode lines of the plurality of gate electrode lines.

公开(公告)号：US11195831B2

公开(公告)日：2021-12-07

申请号：US16596764

申请日：2019-10-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Chen Chiu ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chien-Liang Wu ,  Chih-Kai Kang ,  Guan-Kai Huang

IPC: H01L29/778 ,  H01L27/06 ,  H01L27/085 ,  H01L29/66

Abstract: A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.

公开(公告)号：US20210143214A1

公开(公告)日：2021-05-13

申请号：US16699758

申请日：2019-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Sheng-Yuan Hsueh ,  Ting-Hsiang Huang

IPC: H01L27/22 ,  H01L29/417 ,  H01L23/538 ,  H01L43/12

Abstract: An embedded MRAM structure includes a substrate divided into a memory cell region and a logic device region. An active area is disposed in the memory cell region. A word line is disposed on the substrate and crosses the active area. A source plug is disposed in the active area and at one side of the word line. A drain plug is disposed in the in the active area and at another side of the word line. When viewing from a direction perpendicular to the top surface of the substrate and taking the word line as a symmetric axis, the source plug is a mirror image of the drain plug.