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公开(公告)号：US11944016B2
公开(公告)日：2024-03-26
申请号：US17692203
申请日：2022-03-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A magnetoresistive random access memory, including a substrate, a conductive plug in the substrate, wherein the conductive plug has a notched portion on one side of the upper edge of the conductive plug, and a magnetic memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction on the bottom electrode and a top electrode on the magnetic tunnel junction, wherein the bottom surface of the magnetic memory cell and the top surface of the conductive plug completely align and overlap each other.
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公开(公告)号：US11895848B2
公开(公告)日：2024-02-06
申请号：US17750386
申请日：2022-05-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ya-Huei Tsai , Rai-Min Huang , Yu-Ping Wang , Hung-Yueh Chen
CPC classification number: H10B61/22 , H01L23/528 , H10N50/80 , G11C11/161 , H01F10/3254 , H10N50/85
Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.
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公开(公告)号：US20230403941A1
公开(公告)日：2023-12-14
申请号：US18238520
申请日：2023-08-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-kai Hsu , Hung-Yueh Chen , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to and directly contacting the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is a single layer structure made of dielectric material and an edge of the cap layer contacts the first IMD layer directly.
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公开(公告)号：US11737285B2
公开(公告)日：2023-08-22
申请号：US17202296
申请日：2021-03-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Po-Kai Hsu , Hui-Lin Wang , Kun-I Chou , Ching-Hua Hsu , Ju-Chun Fan , Yi-Yu Lin , Hung-Yueh Chen
Abstract: A memory array includes at least one strap region having therein a plurality of source line straps and a plurality of word line straps, and at least two sub-arrays having a plurality of staggered, active magnetic storage elements. The at least two sub-arrays are separated by the strap region. A plurality of staggered, dummy magnetic storage elements is disposed within the strap region.
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公开(公告)号：US20230240151A1
公开(公告)日：2023-07-27
申请号：US18122730
申请日：2023-03-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Si-Han Tsai , Che-Wei Chang , Po-Kai Hsu , Jing-Yin Jhang , Yu- Ping Wang , Ju-Chun Fan , Ching-Hua Hsu , Yi-Yu Lin , Hung-Yueh Chen
Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.
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Patent Agency Ranking
公开(公告)号：US20220285437A1
公开(公告)日：2022-09-08
申请号：US17750386
申请日：2022-05-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ya-Huei Tsai , Rai-Min Huang , Yu-Ping Wang , Hung-Yueh Chen
IPC: H01L27/22 , H01L23/528 , H01L43/02
Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region, a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, a first magnetic tunneling junction (MTJ) between the first gate pattern and the second pattern and within the word line connecting region, and a second MTJ between the first gate pattern and the second gate pattern in the first active region. Preferably, top surfaces of the first MTJ and the second MTJ are coplanar.
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公开(公告)号：US20220271088A1
公开(公告)日：2022-08-25
申请号：US17202296
申请日：2021-03-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Po-Kai Hsu , Hui-Lin Wang , Kun-I Chou , Ching-Hua Hsu , Ju-Chun Fan , Yi-Yu Lin , Hung-Yueh Chen
Abstract: A memory array includes at least one strap region having therein a plurality of source line straps and a plurality of word line straps, and at least two sub-arrays having a plurality of staggered, active magnetic storage elements. The at least two sub-arrays are separated by the strap region. A plurality of staggered, dummy magnetic storage elements is disposed within the strap region.
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公开(公告)号：US20220263017A1
公开(公告)日：2022-08-18
申请号：US17738001
申请日：2022-05-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Hung-Yueh Chen , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to and directly contacting the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is a single layer structure made of dielectric material and an edge of the cap layer contacts the first IMD layer directly.
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公开(公告)号：US20220263016A1
公开(公告)日：2022-08-18
申请号：US17736069
申请日：2022-05-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Hung-Yueh Chen , Yu-Ping Wang
Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack for forming a first MTJ; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and performing a second patterning process to remove the first MTJ for forming a second MTJ and a third MTJ.
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公开(公告)号：US20220115587A1
公开(公告)日：2022-04-14
申请号：US17090859
申请日：2020-11-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Ju-Chun Fan , Yi-Yu Lin , Ching-Hua Hsu , Hung-Yueh Chen
Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.
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