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公开(公告)号：US20080197418A1
公开(公告)日：2008-08-21
申请号：US11707820
申请日：2007-02-16
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/77 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/42372 , H01L29/4238 , H01L29/7811 , H01L2924/13055 , H01L2924/19043
摘要： In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译： 在一个实施例中，晶体管包括以跑道形布置布置的半导体材料柱，其具有在第一横向方向上延伸的基本上线性的部分，并且在基本线性部分的每个端部处具有圆形部分。 第一和第二电介质区域设置在柱的相对侧上。 第一和第二场板分别设置在第一和第二电介质区域中。 分别设置在第一和第二电介质区域中的第一和第二栅极部件通过在基本线性部分中具有第一厚度的栅极氧化物与柱分离。 栅极氧化物在圆形部分处基本上更厚。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。
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公开(公告)号：US20080197417A1
公开(公告)日：2008-08-21
申请号：US11707406
申请日：2007-02-16
IPC分类号： H01L29/78
CPC分类号： H01L27/088 , H01L21/77 , H01L23/562 , H01L29/0607 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a transistor fabricated on a semiconductor die includes a first section of transistor segments disposed in a first area of the semiconductor die, and a second section of transistor segments disposed in a second area of the semiconductor die adjacent the first area. Each of the transistor segments in the first and second sections includes a pillar of a semiconductor material that extends in a vertical direction. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. Outer field plates of transistor segments adjoining first and second sections are either separated or partially merged. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译： 在一个实施例中，制造在半导体管芯上的晶体管包括设置在半导体管芯的第一区域中的晶体管段的第一部分和设置在邻近第一区域的半导体管芯的第二区域中的晶体管段的第二部分。 第一和第二部分中的每个晶体管段包括在垂直方向上延伸的半导体材料的柱。 第一和第二电介质区域设置在柱的相对侧上。 第一和第二场板分别设置在第一和第二电介质区域中。 邻接第一和第二部分的晶体管段的外场板被分离或部分合并。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。
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公开(公告)号：US20080197406A1
公开(公告)日：2008-08-21
申请号：US11707586
申请日：2007-02-16
IPC分类号： H01L31/00
CPC分类号： H01L29/7815 , H01L29/0696 , H01L29/407 , H01L29/7813
摘要： In one embodiment, a semiconductor device includes a main vertical field-effect transistor (FET) and a sensing FET. The main vertical FET and the sense FET are both formed on a pillar of semiconductor material. Both share an extended drain region formed in the pillar above the substrate, and first and second gate members formed in a dielectric on opposite sides of the pillar. The source regions of the main vertical FET and the sensing FET are separated and electrically isolated in a first lateral direction. In operation, the sensing FET samples a small portion of a current that flows in the main vertical FET. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译： 在一个实施例中，半导体器件包括主垂直场效应晶体管（FET）和感测FET。 主垂直FET和感测FET都形成在半导体材料的柱上。 两者共同地形成在衬底上方的柱中的延伸漏极区域，以及形成在柱的相对侧上的电介质中的第一和第二栅极构件。 主垂直FET和感测FET的源极区域在第一横向方向上分离并电隔离。 在操作中，感测FET对在主垂直FET中流动的电流的一小部分进行采样。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。
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公开(公告)号：US20080197397A1
公开(公告)日：2008-08-21
申请号：US11707418
申请日：2007-02-16
IPC分类号： H01L29/78
CPC分类号： H01L27/0211 , H01L27/0207 , H01L29/0696 , H01L29/0878 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7811 , H01L29/7813
摘要： In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
摘要翻译： 在一个实施例中，制造在半导体管芯上的晶体管被布置成细长晶体管段的部分。 这些部分基本上跨越半导体管芯排列成行和列。 一行或一列的相邻部分定向成使得相邻部分中的第一个部分中的晶体管段的长度在第一方向上延伸，并且相邻部分中的第二个中的晶体管段的长度在 第二方向，第一方向基本上与第二方向正交。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。
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公开(公告)号：US07309638B2
公开(公告)日：2007-12-18
申请号：US11182597
申请日：2005-07-14
CPC分类号： H01L29/866 , H01L27/0255 , H01L27/0814 , Y10S438/983
摘要： A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.
摘要翻译： 半导体部件包括第一半导体区域（110,310），第一半导体区域上方的第二半导体区域（120,320），第二半导体区域上方的第三半导体区域（130,330），第四半导体区域（140,320） ，340），在所述第二半导体区域上方并且与所述第四半导体区域至少部分邻接的第五半导体区域（150,350），在所述第三半导体区域上方的第六半导体区域（160,360），并且电气短路到所述第五半导体区域 半导体区域，以及位于第四半导体区域和第五半导体区域上方的电绝缘层（180,380）。 在第四半导体区域和第五半导体区域之间的结（145,345）形成仅位于电绝缘层下方的齐纳二极管结。 在一个实施例中，第七半导体区域（170）围绕第三，第四，第五和第六半导体区域。
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公开(公告)号：US07282386B2
公开(公告)日：2007-10-16
申请号：US11117996
申请日：2005-04-29
IPC分类号： H01L21/00
CPC分类号： H01L29/872 , H01L29/063 , H01L29/0692 , H01L29/66136 , H01L29/66143 , H01L29/8611
摘要： A Schottky device having a plurality of unit cells, each having a Schottky contact portion, surrounded by a termination structure that causes depletion regions to form in a vertical and horizontal direction, relative to a surface of the device, during a reverse bias voltage condition.
摘要翻译： 肖特基器件具有多个单元电池，每个单元电池具有肖特基接触部分，由反向偏置电压条件期间相对于器件的表面在垂直和水平方向上形成耗尽区域的端接结构包围。
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公开(公告)号：US20060244081A1
公开(公告)日：2006-11-02
申请号：US11426815
申请日：2006-06-27
申请人： Ronghua Zhu , Amitava Bose , Vishnu Khemka , Vijay Parthasarathy
发明人： Ronghua Zhu , Amitava Bose , Vishnu Khemka , Vijay Parthasarathy
IPC分类号： H01L29/76
CPC分类号： H01L29/7391 , H01L29/861
摘要： In one embodiment, semiconductor device 10 comprises a diode which uses isolation regions (34, 16, and 13) and a plurality of dopant concentrations (30, 20, 24, and 26) which may be used to limit the parasitic current that is injected into the semiconductor substrate (12). Various biases on the isolation regions (34, 16, and 13) may be used to affect the behavior of semiconductor device (10). In addition, a conductive layer (28) may be formed overlying the junction between anode (42) and cathode (40). This conductive layer (28) may decrease the electric field in selected regions in order to increase the maximum voltage that may be applied to cathode (40).
摘要翻译： 在一个实施例中，半导体器件10包括使用隔离区域（34,16和13）和多个掺杂剂浓度（30,20,24和26）的二极管，其可用于限制注入的寄生电流 进入半导体基板（12）。 可以使用隔离区域（34,16和13）上的各种偏压来影响半导体器件（10）的行为。 此外，可以形成覆盖在阳极（42）和阴极（40）之间的连接处的导电层（28）。 为了增加施加到阴极（40）的最大电压，该导电层（28）可以减小选定区域中的电场。
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公开(公告)号：US20060014342A1
公开(公告)日：2006-01-19
申请号：US11182597
申请日：2005-07-14
IPC分类号： H01L21/8234 , H01L21/8222 , H01L21/20
CPC分类号： H01L29/866 , H01L27/0255 , H01L27/0814 , Y10S438/983
摘要： A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.
摘要翻译： 半导体部件包括第一半导体区域（110,310），第一半导体区域上方的第二半导体区域（120,320），第二半导体区域上方的第三半导体区域（130,330），第四半导体区域（140,320） ，340），在所述第二半导体区域上方并且与所述第四半导体区域至少部分邻接的第五半导体区域（150,350），在所述第三半导体区域上方的第六半导体区域（160,360），并且电气短路到所述第五半导体区域 半导体区域，以及位于第四半导体区域和第五半导体区域上方的电绝缘层（180,380）。 在第四半导体区域和第五半导体区域之间的结（145,345）形成仅位于电绝缘层下方的齐纳二极管结。 在一个实施例中，第七半导体区域（170）围绕第三，第四，第五和第六半导体区域。
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公开(公告)号：US20060001057A1
公开(公告)日：2006-01-05
申请号：US10881678
申请日：2004-06-30
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L29/80 , H01L21/338
CPC分类号： H01L29/66143 , H01L29/812 , H01L29/872
摘要： A conductive layer includes a first portion that forms a Schottky region with an underlying first region having a first conductivity type. A second region of a second conductivity type underlies the first region, where the second conductivity type is opposite the first conductivity type. A third region of the first conductivity type immediately underlies the second region and is electrically coupled to a cathode of the device.
摘要翻译： 导电层包括形成具有第一导电类型的下面的第一区域的肖特基区域的第一部分。 第二导电类型的第二区域位于第一区域的正下方，其中第二导电类型与第一导电类型相反。 第一导电类型的第三区域刚好在第二区域的下面，并且电耦合到器件的阴极。
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公开(公告)号：US06573562B2
公开(公告)日：2003-06-03
申请号：US10004186
申请日：2001-10-31
IPC分类号： H01L2976
CPC分类号： H03K17/08 , H01L21/761 , H01L27/0629 , H01L27/0635 , H01L27/0664 , H01L27/0676 , H01L27/0814 , H01L29/1083 , H01L29/1087 , H01L29/7835 , H01L29/8611 , H01L29/866
摘要： A semiconductor component includes a semiconductor substrate (110) having first and second portions (111, 112) with a first conductivity type, a transistor (120) at least partially located in the semiconductor substrate, and a switching circuit (150, 350, 650, 850). The transistor includes (i) a first doped region in the first portion of the semiconductor substrate and having the first conductivity type (ii) a terminal, which includes a second doped region having a second conductivity type and located in the first portion of the semiconductor substrate and over the first doped region, and (iii) a third doped region having the second conductivity type and located in the semiconductor substrate below the first portion of the semiconductor substrate and above the second portion of the semiconductor substrate. The switching circuit is electrically coupled to the third doped region to adjust the bias of the third doped region.
摘要翻译： 半导体元件包括具有第一导电类型的第一和第二部分（111,112）的半导体衬底（110），至少部分地位于半导体衬底中的晶体管（120）和开关电路（150,350,650 ，850）。 晶体管包括（i）半导体衬底的第一部分中的第一掺杂区域，并具有第一导电类型（ii）端子，其包括具有第二导电类型并位于半导体的第一部分中的第二掺杂区域 衬底并且在第一掺杂区域上方，以及（iii）具有第二导电类型并且位于半导体衬底的第一部分下方并位于半导体衬底的第二部分之下的第三掺杂区域。 开关电路电耦合到第三掺杂区域以调节第三掺杂区域的偏置。
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