公开(公告)号：US20110310653A1

公开(公告)日：2011-12-22

申请号：US13157191

申请日：2011-06-09

申请人： Franz Kreupl ,  Xiying Costa ,  James Kai ,  Raghuveer S. Makala

发明人： Franz Kreupl ,  Xiying Costa ,  James Kai ,  Raghuveer S. Makala

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L27/2409 ,  G11C11/16 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.

摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。 每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。 第一和第二电阻切换层都可以具有双极或单极开关特性。 在存储单元的置位或复位操作中，跨越第一和第二电极施加电场。 离子电流在电阻切换层中流动，有助于切换机构。 由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。 提供了用于RSME不同层的材料和材料的组合。

公开(公告)号：US07279410B1

公开(公告)日：2007-10-09

申请号：US10379757

申请日：2003-03-05

申请人： Lynne A. Okada ,  Fei Wang ,  James Kai

发明人： Lynne A. Okada ,  Fei Wang ,  James Kai

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/311

CPC分类号： H01L21/76832 ,  H01L21/76802 ,  H01L21/76829

摘要： A method for forming an inlaid interconnect structure for ICs. The method includes forming an etch stop layer, opening a portion of the etch stop layer on an IC die, forming a dielectric layer and cap layer over the etch stop layer, forming a photoresist pattern, and etching the cap and dielectric to form an opening that is then filled with a conductive material (e.g., metal). The method may further include forming a barrier layer within the opening of the etch stop layer. According to another aspect of the invention, a first and second etch stop layer are formed over the substrate and the second etch stop layer is patterned to define two regions, wherein a second region having the first and second etch stop layers experiences a faster etch rate than the first region. The dielectric layer and cap layers are then deposited over both regions and two via or trench openings are formed therethrough in the regions, respectively. The first and second etch stop layers protect the underlying substrate from experiencing punchthrough during the via or trench formation. The etch stop layers are then removed in the openings and a conductive material is formed therein.

摘要翻译： 一种用于形成用于IC的镶嵌互连结构的方法。 该方法包括形成蚀刻停止层，在IC管芯上打开蚀刻停止层的一部分，在蚀刻停止层上形成介电层和覆盖层，形成光致抗蚀剂图案，以及蚀刻帽和电介质以形成开口 然后用导电材料（例如金属）填充。 该方法还可以包括在蚀刻停止层的开口内形成阻挡层。 根据本发明的另一方面，在衬底上形成第一和第二蚀刻停止层，并且将第二蚀刻停止层图案化以限定两个区域，其中具有第一和第二蚀刻停止层的第二区域经历更快的蚀刻速率 比第一个地区。 然后将介电层和盖层沉积在两个区域上，并且分别在区域中形成两个通孔或沟槽开口。 第一和第二蚀刻停止层在通孔或沟槽形成期间保护下面的衬底不经历穿透。 然后在开口中去除蚀刻停止层，并在其中形成导电材料。

公开(公告)号：US08520424B2

公开(公告)日：2013-08-27

申请号：US13157204

申请日：2011-06-09

申请人： Franz Kreupl ,  Abhijit Bandyopadhyay ,  Yung-Tin Chen ,  Chu-Chen Fu ,  Wipul Pemsiri Jayasekara ,  James Kai ,  Raghuveer S. Makala ,  Peter Rabkin ,  George Samachisa ,  Jingyan Zhang

发明人： Franz Kreupl ,  Abhijit Bandyopadhyay ,  Yung-Tin Chen ,  Chu-Chen Fu ,  Wipul Pemsiri Jayasekara ,  James Kai ,  Raghuveer S. Makala ,  Peter Rabkin ,  George Samachisa ,  Jingyan Zhang

IPC分类号： G11C11/00

CPC分类号： H01L27/2409 ,  G11C11/16 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.

摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。 每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。 第一和第二电阻切换层都可以具有双极或单极开关特性。 在存储单元的置位或复位操作中，离子电流在电阻切换层中流动，有助于切换机构。 由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。 提供了用于RSME不同层的材料和材料的组合。

公开(公告)号：US06767827B1

公开(公告)日：2004-07-27

申请号：US10459328

申请日：2003-06-11

申请人： Lynne A. Okada ,  Fei Wang ,  James Kai

发明人： Lynne A. Okada ,  Fei Wang ,  James Kai

IPC分类号： H01L214763

CPC分类号： H01L21/76832 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L2221/1063

摘要： A method for forming a dual inlaid interconnect structure for ICs is disclosed. The method includes forming an etch stop layer, opening a portion of the etch stop layer on an IC die, forming a first dielectric layer, a middle stop layer, a second dielectric layer and a cap layer thereover. The method further comprises patterning the cap, dielectric layers and middle stop layer a via opening down to the etch stop layer that is associated with the opening therein. A trench opening is formed down through the cap and second dielectric layer and stopping on the middle stop layer. The trench/via opening is then filled with a conductive material (e.g., metal). The method may further include forming a barrier layer within the opening of the etch stop layer. According to another aspect of the invention, a first and second etch stop layer are formed over the substrate and the second etch stop layer is patterned to define two regions, wherein a second region having the first and second etch stop layers experiences a faster etch rate than the first region. The first dielectric layer, middle stop layer, second dielectric layer and cap layer are then deposited over both regions and two via openings are formed therethrough in the regions, respectively. The first and second etch stop layers protect the underlying substrate from experiencing punchthrough during the via formation. A trench pattern is then defined in the second dielectric layer and the etch stop layers are then removed in the openings and a conductive material is formed therein.

摘要翻译： 公开了一种形成用于IC的双镶嵌互连结构的方法。 该方法包括形成蚀刻停止层，在IC管芯上打开蚀刻停止层的一部分，在其上形成第一介电层，中间停止层，第二介电层和盖层。 该方法还包括将盖，电介质层和中间停止层的图形图案化，通孔向下通向与其中的开口相关联的蚀刻停止层。 通过盖和第二介电层向下形成沟槽开口，并在中间停止层上停止。 然后用导电材料（例如金属）填充沟槽/通孔开口。 该方法还可以包括在蚀刻停止层的开口内形成阻挡层。 根据本发明的另一方面，在衬底上形成第一和第二蚀刻停止层，并且将第二蚀刻停止层图案化以限定两个区域，其中具有第一和第二蚀刻停止层的第二区域经历更快的蚀刻速率 比第一个地区。 然后在两个区域上沉积第一介电层，中间阻挡层，第二介电层和盖层，并且在该区域中分别形成两个通孔。 第一和第二蚀刻停止层在通孔形成期间保护下面的衬底不经历穿透。 然后在第二电介质层中限定沟槽图案，然后在开口中去除蚀刻停止层，并在其中形成导电材料。