公开(公告)号：USRE37505E1

公开(公告)日：2002-01-15

申请号：US08628287

申请日：1996-04-05

申请人： Guy Blalock ,  Phillip G. Wald

发明人： Guy Blalock ,  Phillip G. Wald

IPC分类号： H01L2978

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L28/84 ,  H01L28/91 ,  Y10S438/964

摘要： A method of forming a capacitor on a semiconductor wafer includes: a) in a dry etching reactor, selectively anisotropically dry etching a capacitor contact opening having a minimum selected open dimension into an insulating dielectric layer utilizing selected gas flow rates of a reactive gas component and an inert gas bombarding component, the flow rate of the bombarding component significantly exceeding the flow rate of the reactive component to effectively produce a capacitor contact opening having grooved striated sidewalls and thereby defining female capacitor contact opening striations; b) providing a layer of an electrically conductive storage node material within the striated capacitor contact opening; c) removing at least a portion of the conductive material layer to define an isolated capacitor storage node within the insulating dielectric having striated sidewalls; d) etching the insulating dielectric layer selectively relative to the conductive material sufficiently to expose at least a portion of the external male striated conductive material sidewalls; and e) providing conformal layers of capacitor dielectric and capacitor cell material atop the etched conductive material and over its exposed striated sidewalls. The invention also includes a stacked capacitor construction having an electrically conductive storage node with upwardly rising external sidewalls. Such sidewalls have longitudinally extending striations to maximize surface area and corresponding capacitance in a resulting construction.

摘要翻译： 在半导体晶片上形成电容器的方法包括：a）在干式蚀刻反应器中，利用选择的反应性气体组分的气体流速，选择性地各向异性地将具有最小选定开口尺寸的电容器接触开口刻蚀成绝缘介电层;以及 惰性气体轰击组分，轰击组分的流速显着超过反应组分的流速，以有效地产生具有沟槽条纹侧壁的电容器接触开口，从而限定母电容器接触开口条纹; b）在条纹电容器接触开口内提供导电存储节点材料层; c）去除所述导电材料层的至少一部分以在所述绝缘电介质内限定具有条纹侧壁的隔离电容器存储节点; d）相对于导电材料选择性地蚀刻绝缘介电层，足以露出至少一部分外部凸纹状导电材料侧壁; 以及e）在蚀刻的导电材料的顶部和其暴露的条纹侧壁上提供电容器电介质和电容器电池材料的保形层。 本发明还包括具有具有向上升高的外侧壁的导电存储节点的堆叠电容器结构。 这样的侧壁具有纵向延伸的条纹，以在最终结构中最大化表面积和相应的电容。

公开(公告)号：US6153527A

公开(公告)日：2000-11-28

申请号：US441718

申请日：1999-11-16

申请人： Mark E. Jost ,  Phillip G. Wald

发明人： Mark E. Jost ,  Phillip G. Wald

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L27/105 ,  H01L27/108 ,  H01L21/311

CPC分类号： H01L27/10844 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76885 ,  H01L23/485 ,  H01L27/105 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002

摘要： A semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material includes, a) providing a node within a mass of insulating dielectric material; b) first stage etching into the insulating dielectric material over the node in a manner substantially selective relative to the node; c) after the first stage etching, second stage etching the dielectric material in a manner which increases a degree of sidewall polymerization over that occurring in the first stage etching and in a manner substantially selective relative to the node; and d) after the second stage etching, third stage etching the dielectric material with a degree of sidewall polymerization which is less than that of the second stage etching and in a manner substantially selective relative to the first node. An alternate method provides an etch stop annulus cap 70 overlying an electrically conductive ring 62 which projects from a primary insulating layer 54. A secondary insulating 74 is then provided outwardly of the etch stop annulus cap. A second contact opening 76 is patterned and etched through the second insulating layer relative to the first contact opening and to the etch stop annulus cap, with the second contact opening having a wider target area 80 than would otherwise be provided if the annulus cap were not present. Aspects of the invention have significant utility in the fabrication of bit line over capacitor arrays of memory cells.

摘要翻译： 对接收在绝缘介电材料块内的节点进行电接触的半导体处理方法包括：a）在绝缘介电材料块内提供节点; b）以相对于节点基本上选择性的方式在节点上第一级蚀刻到绝缘介电材料中; c）在第一阶段蚀刻之后，第二阶段以相对于该节点基本上选择性的方式，以增加与第一阶段蚀刻中发生的侧壁聚合程度相似的方式来蚀刻电介质材料; 以及d）在第二阶段蚀刻之后，第三阶段以比第二阶段蚀刻小的侧壁聚合程度以相对于第一节点基本选择的方式蚀刻电介质材料。 替代方法提供了覆盖从主绝缘层54突出的导电环62的蚀刻阻挡环盖70.然后在蚀刻停止环形盖的外侧设置次级绝缘体74。 第二接触开口76相对于第一接触开口和蚀刻停止环形盖被图案化和蚀刻通过第二绝缘层，其中第二接触开口具有比否则将提供的更宽的目标区域80 当下。 本发明的方面在存储器单元的电容器阵列上的位线的制造中具有显着的用途。

公开(公告)号：US6037261A

公开(公告)日：2000-03-14

申请号：US28045

申请日：1998-02-23

申请人： Mark E. Jost ,  Phillip G. Wald

发明人： Mark E. Jost ,  Phillip G. Wald

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L27/105 ,  H01L27/108 ,  H01L21/3065

CPC分类号： H01L27/10844 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76885 ,  H01L23/485 ,  H01L27/105 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002

摘要： A semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material includes, a) providing a node within a mass of insulating dielectric material; b) first stage etching into the insulating dielectric material over the node in a manner substantially selective relative to the node; c) after the first stage etching, second stage etching the dielectric material in a manner which increases a degree of sidewall polymerization over that occurring in the first stage etching and in a manner substantially selective relative to the node; and d) after the second stage etching, third stage etching the dielectric material with a degree of sidewall polymerization which is less than that of the second stage etching and in a manner substantially selective relative to the first node. An alternate method provides an etch stop annulus cap overlying an electrically conductive ring which projects from a primary insulating layer. A secondary insulating layer is then provided outwardly of the etch stop annulus cap. A second contact opening is patterned and etched through the second insulating layer relative to the first contact opening and to the etch stop annulus cap, with the second contact opening having a wider target area than would otherwise be provided if the annulus cap were not present. Aspects of the invention have significant utility in the fabrication of bit line over capacitor arrays of memory cells.

摘要翻译： 对接收在绝缘介电材料块内的节点进行电接触的半导体处理方法包括：a）在绝缘介电材料块内提供节点; b）以相对于节点基本上选择性的方式在节点上第一级蚀刻到绝缘介电材料中; c）在第一阶段蚀刻之后，第二阶段以相对于该节点基本上选择性的方式，以增加与第一阶段蚀刻中发生的侧壁聚合程度相似的方式来蚀刻电介质材料; 以及d）在第二阶段蚀刻之后，第三阶段以比第二阶段蚀刻小的侧壁聚合程度以相对于第一节点基本选择的方式蚀刻电介质材料。 替代方法提供覆盖从主绝缘层突出的导电环的蚀刻停止环形覆盖层。 然后在蚀刻停止环形盖的外侧设置次级绝缘层。 第二接触开口相对于第一接触开口和蚀刻停止环形盖通过第二绝缘层图案化并蚀刻，其中第二接触开口具有比否则将提供的环面帽不存在时更宽的目标面积。 本发明的方面在存储器单元的电容器阵列上的位线的制造中具有显着的用途。