公开(公告)号：US5739068A

公开(公告)日：1998-04-14

申请号：US595595

申请日：1996-02-02

申请人： Mark E. Jost ,  Phillip G. Wald

发明人： Mark E. Jost ,  Phillip G. Wald

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L27/105 ,  H01L27/108 ,  H01L21/4763

CPC分类号： H01L27/10844 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76885 ,  H01L23/485 ,  H01L27/105 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002

摘要： A semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material includes, a) providing a node within a mass of insulating dielectric material; b) first stage etching into the insulating dielectric material over the node in a manner substantially selective relative to the node; c) after the first stage etching, second stage etching the dielectric material in a manner which increases a degree of sidewall polymerization over that occurring in the first stage etching and in a manner substantially selective relative to the node; and d) after the second stage etching, third stage etching the dielectric material with a degree of sidewall polymerization which is less than that of the second stage etching and in a manner substantially selective relative to the first node. An alternate method provides an etch stop annulus cap overlying an electrically conductive ring which projects from a primary insulating layer. A secondary insulating layer is then provided outwardly of the etch stop annulus cap. A second contact opening is patterned and etched through the second insulating layer relative to the first contact opening and to the etch stop annulus cap, with the second contact opening having a wider target area than would otherwise be provided if the annulus cap were not present. Aspects of the invention have significant utility in the fabrication of bit line over capacitor arrays of memory cells.

公开(公告)号：US6153527A

公开(公告)日：2000-11-28

申请号：US441718

申请日：1999-11-16

申请人： Mark E. Jost ,  Phillip G. Wald

发明人： Mark E. Jost ,  Phillip G. Wald

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L27/105 ,  H01L27/108 ,  H01L21/311

CPC分类号： H01L27/10844 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76885 ,  H01L23/485 ,  H01L27/105 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002

摘要： A semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material includes, a) providing a node within a mass of insulating dielectric material; b) first stage etching into the insulating dielectric material over the node in a manner substantially selective relative to the node; c) after the first stage etching, second stage etching the dielectric material in a manner which increases a degree of sidewall polymerization over that occurring in the first stage etching and in a manner substantially selective relative to the node; and d) after the second stage etching, third stage etching the dielectric material with a degree of sidewall polymerization which is less than that of the second stage etching and in a manner substantially selective relative to the first node. An alternate method provides an etch stop annulus cap 70 overlying an electrically conductive ring 62 which projects from a primary insulating layer 54. A secondary insulating 74 is then provided outwardly of the etch stop annulus cap. A second contact opening 76 is patterned and etched through the second insulating layer relative to the first contact opening and to the etch stop annulus cap, with the second contact opening having a wider target area 80 than would otherwise be provided if the annulus cap were not present. Aspects of the invention have significant utility in the fabrication of bit line over capacitor arrays of memory cells.

摘要翻译： 对接收在绝缘介电材料块内的节点进行电接触的半导体处理方法包括：a）在绝缘介电材料块内提供节点; b）以相对于节点基本上选择性的方式在节点上第一级蚀刻到绝缘介电材料中; c）在第一阶段蚀刻之后，第二阶段以相对于该节点基本上选择性的方式，以增加与第一阶段蚀刻中发生的侧壁聚合程度相似的方式来蚀刻电介质材料; 以及d）在第二阶段蚀刻之后，第三阶段以比第二阶段蚀刻小的侧壁聚合程度以相对于第一节点基本选择的方式蚀刻电介质材料。 替代方法提供了覆盖从主绝缘层54突出的导电环62的蚀刻阻挡环盖70.然后在蚀刻停止环形盖的外侧设置次级绝缘体74。 第二接触开口76相对于第一接触开口和蚀刻停止环形盖被图案化和蚀刻通过第二绝缘层，其中第二接触开口具有比否则将提供的更宽的目标区域80 当下。 本发明的方面在存储器单元的电容器阵列上的位线的制造中具有显着的用途。

公开(公告)号：US6037261A

公开(公告)日：2000-03-14

申请号：US28045

申请日：1998-02-23

申请人： Mark E. Jost ,  Phillip G. Wald

发明人： Mark E. Jost ,  Phillip G. Wald

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L27/105 ,  H01L27/108 ,  H01L21/3065

CPC分类号： H01L27/10844 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76885 ,  H01L23/485 ,  H01L27/105 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/82 ,  H01L28/84 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002

摘要： A semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material includes, a) providing a node within a mass of insulating dielectric material; b) first stage etching into the insulating dielectric material over the node in a manner substantially selective relative to the node; c) after the first stage etching, second stage etching the dielectric material in a manner which increases a degree of sidewall polymerization over that occurring in the first stage etching and in a manner substantially selective relative to the node; and d) after the second stage etching, third stage etching the dielectric material with a degree of sidewall polymerization which is less than that of the second stage etching and in a manner substantially selective relative to the first node. An alternate method provides an etch stop annulus cap overlying an electrically conductive ring which projects from a primary insulating layer. A secondary insulating layer is then provided outwardly of the etch stop annulus cap. A second contact opening is patterned and etched through the second insulating layer relative to the first contact opening and to the etch stop annulus cap, with the second contact opening having a wider target area than would otherwise be provided if the annulus cap were not present. Aspects of the invention have significant utility in the fabrication of bit line over capacitor arrays of memory cells.

摘要翻译： 对接收在绝缘介电材料块内的节点进行电接触的半导体处理方法包括：a）在绝缘介电材料块内提供节点; b）以相对于节点基本上选择性的方式在节点上第一级蚀刻到绝缘介电材料中; c）在第一阶段蚀刻之后，第二阶段以相对于该节点基本上选择性的方式，以增加与第一阶段蚀刻中发生的侧壁聚合程度相似的方式来蚀刻电介质材料; 以及d）在第二阶段蚀刻之后，第三阶段以比第二阶段蚀刻小的侧壁聚合程度以相对于第一节点基本选择的方式蚀刻电介质材料。 替代方法提供覆盖从主绝缘层突出的导电环的蚀刻停止环形覆盖层。 然后在蚀刻停止环形盖的外侧设置次级绝缘层。 第二接触开口相对于第一接触开口和蚀刻停止环形盖通过第二绝缘层图案化并蚀刻，其中第二接触开口具有比否则将提供的环面帽不存在时更宽的目标面积。 本发明的方面在存储器单元的电容器阵列上的位线的制造中具有显着的用途。

公开(公告)号：US06903957B2

公开(公告)日：2005-06-07

申请号：US10863070

申请日：2004-06-08

申请人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

发明人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

IPC分类号： G11C11/401 ,  G11C11/404 ,  G11C17/12 ,  G11C17/00

CPC分类号： G11C11/404 ,  G11C17/12 ,  G11C2207/104

摘要： A half-density ROM embedded DRAM uses hard programmed non-volatile cells and unprogrammed dynamic cells. By hard programming either a first or second memory cell in a pair of cell, different data states are stored. Two word lines are used to access the memory cell pair. Because one of the cells is hard programmed, sense amplifier circuitry identifies the appropriate data state. The ROM cell can be programmed in numerous different manners. For example, ROM cells can be hard programmed by eliminating cell dielectric to short cell plates to a program voltage, or an electrical plug can be fabricated between the cell plates and shorted to a program voltage. In other embodiments, the ROM cell can be programmed using an anti-fuse programming technique, or by providing a high leakage path (not full short) such as through an active area to the substrate.

摘要翻译： 半密度ROM嵌入式DRAM使用硬编程的非易失性单元和未编程的动态单元。 通过对一对单元格中的第一或第二存储单元进行硬编程，存储不同的数据状态。 两条字线用于访问存储单元对。 因为其中一个单元是硬编程的，所以读出放大器电路识别适当的数据状态。 ROM单元可以以多种不同的方式进行编程。 例如，ROM单元可以通过将单元电池的电介质消除到编程电压来进行硬编程，或者可以在单元板之间制造电插头并且短路到编程电压。 在其他实施例中，ROM单元可以使用反熔丝编程技术进行编程，或者通过向衬底提供诸如通过有源区域的高泄漏路径（非完全短路）。

公开(公告)号：US06747889B2

公开(公告)日：2004-06-08

申请号：US10017658

申请日：2001-12-12

申请人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

发明人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

IPC分类号： G11C1700

CPC分类号： G11C11/404 ,  G11C17/12 ,  G11C2207/104

摘要： A half-density ROM embedded DRAM uses hard programmed non-volatile cells and unprogrammed dynamic cells. By hard programming either a first or second memory cell in a pair of cell, different data states are stored. Two word lines are used to access the memory cell pair. Because one of the cells is hard programmed, sense amplifier circuitry identifies the appropriate data state. The ROM cell can be programmed in numerous different manners. For example, ROM cells can be hard programmed by eliminating cell dielectric to short cell plates to a program voltage, or an electrical plug can be fabricated between the cell plates and shorted to a program voltage. In other embodiments, the ROM cell can be programmed using an anti-fuse programming technique, or by providing a high leakage path (not full short) such as through an active area to the substrate.

摘要翻译： 半密度ROM嵌入式DRAM使用硬编程的非易失性单元和未编程的动态单元。 通过对一对单元格中的第一或第二存储单元进行硬编程，存储不同的数据状态。 两条字线用于访问存储单元对。 因为其中一个单元是硬编程的，所以读出放大器电路识别适当的数据状态。 ROM单元可以以多种不同的方式进行编程。 例如，ROM单元可以通过将单元电池的电介质消除到编程电压来进行硬编程，或者可以在单元板之间制造电插头并且短路到编程电压。 在其他实施例中，ROM单元可以使用反熔丝编程技术进行编程，或者通过向衬底提供诸如通过有源区域的高泄漏路径（非完全短路）。

公开(公告)号：US06703327B2

公开(公告)日：2004-03-09

申请号：US10128757

申请日：2002-06-13

申请人： Richard H. Lane ,  Phillip G. Wald

发明人： Richard H. Lane ,  Phillip G. Wald

IPC分类号： H01L2100

CPC分类号： H01L21/28185 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/324 ,  H01L29/513 ,  H01L29/518 ,  Y10S438/904 ,  Y10S438/908

摘要： An improved process for annealing integrated circuits to repair fabrication-induced damage. An integrated circuit is annealed in a pressurized sealed chamber in which a forming gas comprising hydrogen is present. Pressurization of the chamber reduces the contribution made by the final anneal step to total thermal exposure by increasing the diffusion rate of the hydrogen into the materials from which the integrated circuit is fabricated. Ideally, the forming gas contains, in addition to hydrogen, at least one other gas such as nitrogen or argon that will not react with hydrogen and, thus, reduces the danger of explosion. However, the integrated circuit may be annealed in an ambiance containing only hydrogen gas that is maintained at a pressure greater than ambient atmospheric pressure.

摘要翻译： 一种用于退火集成电路以修复制造损坏的改进方法。 集成电路在其中存在包含氢的形成气体的加压密封室中退火。 通过增加氢气到制造集成电路的材料的扩散速率，腔室的加压减小了最终退火步骤对总热暴露的贡献。 理想地，除了氢气之外，形成气体还包含至少一种不与氢气反应的其它气体，例如氮气或氩气，从而降低爆炸危险。 然而，集成电路可以仅包含保持在大于环境大气压的压力的氢气的环境中退火。

公开(公告)号：US06545899B1

公开(公告)日：2003-04-08

申请号：US10020371

申请日：2001-12-12

申请人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

发明人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

IPC分类号： G11C1700

CPC分类号： G11C7/14 ,  G11C7/06 ,  G11C17/12 ,  G11C17/18 ,  G11C2207/104

摘要： A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. Further, a differential pre-charge operation can also be used in another embodiment. The ROM embedded DRAM allows for simplifier fabrication and programming of the ROM cells, while providing accurate dual state functionality.

公开(公告)号：US6107189A

公开(公告)日：2000-08-22

申请号：US811488

申请日：1997-03-05

申请人： Phillip G. Wald ,  Kunal R. Parekh

发明人： Phillip G. Wald ,  Kunal R. Parekh

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76895 ,  H01L21/76807 ,  H01L2221/1063

摘要： A semiconductor device including a structure having an upper surface and an contact surface formed at the upper surface of the structure. An insulating material is formed over the contact surface and a conductive runner extends over the active area such that a lower surface of the conductive runner is above and separated from the active area. A widened portion is formed in the conductive runner with an opening formed in the widened portion and self-aligned to edges of the widened portion. A conductive pillar is self-aligned to the opening and extends downward through the opening, through the insulating material, to the active area. The conductive runner provides local interconnection that can be routed over device features formed in and on the structure without using an additional metal layer.

摘要翻译： 一种半导体器件，包括具有形成在该结构的上表面的上表面和接触表面的结构。 在接触表面上形成绝缘材料，并且导电流道在有源区域上延伸，使得导电流道的下表面在有效区域之上并与活性区域分离。 在导电流道中形成加宽部分，其中开口形成在加宽部分中并与加宽部分的边缘自对准。 导电柱与开口自对准，并通过开口向下穿过绝缘材料延伸至有源区。 导电流道提供局部互连，其可以被布置在结构上和结构上形成的器件特征上，而不使用附加的金属层。

公开(公告)号：US5300801A

公开(公告)日：1994-04-05

申请号：US58778

申请日：1993-04-28

申请人： Guy Blalock ,  Phillip G. Wald

发明人： Guy Blalock ,  Phillip G. Wald

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L28/84 ,  H01L28/91 ,  Y10S438/964

摘要： A method of forming a capacitor on a semiconductor wafer includes: a) in a dry etching reactor, selectively anisotropically dry etching a capacitor contact opening having a minimum selected open dimension into an insulating dielectric layer utilizing selected gas flow rates of a reactive gas component and an inert gas bombarding component, the flow rate of the bombarding component significantly exceeding the flow rate of the reactive component to effectively produce a capacitor contact opening having grooved striated sidewalls and thereby defining female capacitor contact opening striations; b) providing a layer of an electrically conductive storage node material within the striated capacitor contact opening; c) removing at least a portion of the conductive material layer to define an isolated capacitor storage node within the insulating dielectric having striated sidewalls; d) etching the insulating dielectric layer selectively relative to the conductive material sufficiently to expose at least a portion of the external male striated conductive material sidewalls; and e) providing conformal layers of capacitor dielectric and capacitor cell material atop the etched conductive material and over its exposed striated sidewalls. The invention also includes a stacked capacitor construction having an electrically conductive storage node with upwardly rising external sidewalls. Such sidewalls have longitudinally extending striations to maximize surface area and corresponding capacitance in a resulting construction.

摘要翻译： 在半导体晶片上形成电容器的方法包括：a）在干式蚀刻反应器中，利用选择的反应性气体组分的气体流速，选择性地各向异性地将具有最小选定开口尺寸的电容器接触开口刻蚀成绝缘介电层;以及 惰性气体轰击组分，轰击组分的流速显着超过反应组分的流速，以有效地产生具有沟槽条纹侧壁的电容器接触开口，从而限定母电容器接触开口条纹; b）在条纹电容器接触开口内提供导电存储节点材料层; c）去除所述导电材料层的至少一部分以在所述绝缘电介质内限定具有条纹侧壁的隔离电容器存储节点; d）相对于导电材料选择性地蚀刻绝缘介电层，足以露出至少一部分外部凸纹状导电材料侧壁; 以及e）在蚀刻的导电材料的顶部和其暴露的条纹侧壁上提供电容器电介质和电容器电池材料的保形层。 本发明还包括具有具有向上升高的外侧壁的导电存储节点的堆叠电容器结构。 这样的侧壁具有纵向延伸的条纹，以在最终结构中最大化表面积和相应的电容。

公开(公告)号：US06771529B2

公开(公告)日：2004-08-03

申请号：US10376768

申请日：2003-02-28

申请人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

发明人： Scott Derner ,  Casey Kurth ,  Phillip G. Wald

IPC分类号： G11C1700

CPC分类号： G11C7/14 ,  G11C7/06 ,  G11C17/12 ,  G11C17/18 ,  G11C2207/104

摘要： A ROM embedded DRAM that provides ROM cells that can be programmed to a single state. Bias techniques are used to read un-programmed ROM cells accurately. Sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. Further, a differential pre-charge operation can also be used in another embodiment. The ROM embedded DRAM allows for simplifier fabrication and programming of the ROM cells, while providing accurate dual state functionality.