公开(公告)号：US06970380B1

公开(公告)日：2005-11-29

申请号：US10711514

申请日：2004-09-23

申请人： Chih-Chieh Yeh ,  Wen-Jer Tsai

发明人： Chih-Chieh Yeh ,  Wen-Jer Tsai

IPC分类号： G11C16/04 ,  G11C16/34

CPC分类号： G11C16/3486 ,  G11C16/3468

摘要： A method for programming a non-volatile memory is described. In the method, a reference level is selected according to the level distribution of the memory cells in a storage state, and then predetermined memory cells are programmed to a next storage state according to the reference level. The reference level falls between the cell level distribution of the storage state and that of the next storage state.

摘要翻译： 描述用于编程非易失性存储器的方法。 在该方法中，根据存储状态下的存储单元的电平分布来选择参考电平，然后根据参考电平将预定存储单元编程到下一个存储状态。 参考电平落在存储状态的单元级别分布和下一个存储状态的单元级别分布之间。

公开(公告)号：US08861281B2

公开(公告)日：2014-10-14

申请号：US13105276

申请日：2011-05-11

申请人： Ping-Hung Tsai ,  Jyun-Siang Huang ,  Wen-Jer Tsai

发明人： Ping-Hung Tsai ,  Jyun-Siang Huang ,  Wen-Jer Tsai

IPC分类号： G11C11/40 ,  G11C16/34 ,  G11C16/32 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/0433 ,  G11C16/32 ,  G11C16/3454

摘要： A method of programming a memory is provided. The memory has a first cell, having a first S/D region and a second S/D region shared with a second cell. The second cell has a third S/D region opposite to the second S/D region. When programming the first cell, a first voltage is applied to a control gate of the first cell, a second voltage is applied to a control gate of the second cell to slightly turn on a channel of the second cell, a third and a fourth voltage are respectively applied to the first and the third S/D regions, and the second S/D region is floating. A carrier flows from the third S/D region to the first S/D region, and is injected into a charge storage layer of the first cell by source-side injection.

摘要翻译： 提供了一种编程存储器的方法。 存储器具有第一单元，具有与第二单元共用的第一S / D区和第二S / D区。 第二单元具有与第二S / D区相反的第三S / D区。 当对第一单元进行编程时，第一电压被施加到第一单元的控制栅极，第二电压被施加到第二单元的控制栅极，以稍微导通第二单元的沟道，第三和第四电压 分别施加到第一和第三S / D区域，并且第二S / D区域是浮置的。 载体从第三S / D区流向第一S / D区，并通过源侧注入注入第一单元的电荷存储层。

公开(公告)号：US08791522B2

公开(公告)日：2014-07-29

申请号：US13271517

申请日：2011-10-12

申请人： Chih-Chieh Cheng ,  Shih-Guei Yan ,  Cheng-Hsien Cheng ,  Wen-Jer Tsai

发明人： Chih-Chieh Cheng ,  Shih-Guei Yan ,  Cheng-Hsien Cheng ,  Wen-Jer Tsai

IPC分类号： H01L29/792

CPC分类号： H01L29/66833 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887 ,  H01L29/7923

摘要： A non-volatile memory and a manufacturing method thereof are provided. A first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the charge storage spacers. A conductive layer is formed on the second oxide layer.

摘要翻译： 提供了一种非易失性存储器及其制造方法。 具有突出部的第一氧化物层形成在基板上。 在突起的两侧在衬底中形成一对掺杂区域。 在突起的侧壁上形成一对电荷存储间隔物。 在第一氧化物层和电荷存储间隔物上形成第二氧化物层。 在第二氧化物层上形成导电层。

公开(公告)号：US08760909B2

公开(公告)日：2014-06-24

申请号：US13277816

申请日：2011-10-20

申请人： Jyun-Siang Huang ,  Wen-Jer Tsai

发明人： Jyun-Siang Huang ,  Wen-Jer Tsai

IPC分类号： G11C11/00

CPC分类号： H01L29/66833 ,  H01L27/11578 ,  H01L29/792

摘要： A memory and a manufacturing method thereof are provided. A plurality of stacked structures extending along a first direction is formed on a substrate. Each of the stacked structures includes a plurality of first insulating layers and a plurality of second insulating layers. The first insulating layers are stacked on the substrate and the second insulating layers are respectively disposed between the adjacent first insulating layers. A plurality of trenches extending along the first direction is formed in each of the stacked structures. The trenches are respectively located at two opposite sides of each of the second insulating layers. A first conductive layer is filled in the trenches. A plurality of charge storage structures extending along a second direction is formed on the stacked structures and a second conductive layer is formed on each of the charge storage structures.

摘要翻译： 提供了一种存储器及其制造方法。 沿着第一方向延伸的多个堆叠结构形成在基板上。 每个堆叠结构包括多个第一绝缘层和多个第二绝缘层。 第一绝缘层层叠在基板上，第二绝缘层分别设置在相邻的第一绝缘层之间。 沿着第一方向延伸的多个沟槽形成在每个堆叠结构中。 沟槽分别位于每个第二绝缘层的两个相对侧。 第一导电层填充在沟槽中。 沿着第二方向延伸的多个电荷存储结构形成在层叠结构上，并且在每个电荷存储结构上形成第二导电层。

公开(公告)号：US08531886B2

公开(公告)日：2013-09-10

申请号：US12797994

申请日：2010-06-10

申请人： Jyun-Siang Huang ,  Wen-Jer Tsai

发明人： Jyun-Siang Huang ,  Wen-Jer Tsai

IPC分类号： G11C11/34

CPC分类号： G11C16/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

摘要： A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection using a boosted channel potential to establish the heating field. Boosted channel hot carrier injection can be based on blocking flow of carriers between a first side of a selected cell and a second side of the selected cell in the NAND string, boosting by capacitive coupling the first semiconductor body region to a boosted voltage level, biasing the second semiconductor body region to a reference voltage level, applying a program potential greater than a hot carrier injection barrier level to the selected cell and enabling flow of carriers from the second semiconductor body region to the selected cell to cause generation of hot carriers.

摘要翻译： 存储器件包括串联布置在半导体本体中的多个存储单元，例如具有多个字线的NAND串。 通过使用升压通道电位的热载流子注入来对选定的存储单元进行编程以建立加热场。 升压通道热载流子注入可以基于阻塞NAND串中选定单元的第一侧和所选单元的第二侧之间的载流子的流动，通过将第一半导体体区域电容耦合到提升的电压电平来提升 将第二半导体主体区域设置为参考电压电平，将大于热载流子注入势垒级的编程电位施加到所选择的单元，并且使载流子能够从第二半导体体区域流向所选择的单元以引起热载流子的产生。

公开(公告)号：US08369148B2

公开(公告)日：2013-02-05

申请号：US12264893

申请日：2008-11-04

申请人： Tien-Fan Ou ,  Wen-Jer Tsai ,  Jyun-Siang Huang

发明人： Tien-Fan Ou ,  Wen-Jer Tsai ,  Jyun-Siang Huang

IPC分类号： G11C11/34

CPC分类号： G11C5/04 ,  G11C16/0416 ,  G11C16/10 ,  H01L27/11521 ,  H01L27/11568

摘要： An integrated circuit includes a memory cell structure including a first cell and a second cell. The first cell includes a first storage structure and a first gate over a substrate. The first gate is over the first storage structure. The second cell includes a second storage structure and a second gate over the substrate. The second gate is over the second storage structure. The first gate is separated from the second gate. A first doped region is adjacent to the first cell and is coupled to a first source. A second doped region is configured within the substrate and adjacent to the second cell. The second doped region is coupled to a second source. At least one third doped region is between the first cell and the second cell, wherein the third doped region is floating.

摘要翻译： 集成电路包括包括第一单元和第二单元的存储单元结构。 第一单元包括第一存储结构和衬底上的第一栅极。 第一个门是第一个存储结构。 第二单元包括第二存储结构和衬底上的第二栅极。 第二个门是第二个存储结构。 第一个门与第二个门分开。 第一掺杂区域与第一单元相邻并且耦合到第一源极。 第二掺杂区域被配置在衬底内且与第二单元相邻。 第二掺杂区域耦合到第二源极。 至少一个第三掺杂区域在第一单元和第二单元之间，其中第三掺杂区域是浮置的。

公开(公告)号：US08369140B2

公开(公告)日：2013-02-05

申请号：US12018709

申请日：2008-01-23

申请人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Yi-Ying Liao

发明人： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Yi-Ying Liao

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C11/5671 ,  G11C16/0483 ,  G11C2211/5621

摘要： A multi-Level Cell (MLC) can be used to store, for example, 4 bits per cell by storing two bits on each of two sides. Each side can store, e.g., four different current level states that can be determined by the number of holes injected into, e.g., nitride layer, during programming. As more holes are injected the current decreases for a given voltage. The current can be low, therefore, it can be advantageous in one embodiment to use a current amplifier. The current amplifier can be a BJT, MOS or other type of device.

摘要翻译： 多级单元（MLC）可用于通过在两侧存储两位来存储例如每单元4位。 每一侧都可以存储例如四个不同的电流状态，这些状态可以通过在编程期间注入到例如氮化物层中的空穴的数量来确定。 随着更多的孔被注入，给定电压的电流减小。 电流可能很低，因此，在一个实施例中使用电流放大器可能是有利的。 电流放大器可以是BJT，MOS或其他类型的器件。

公开(公告)号：US20120326222A1

公开(公告)日：2012-12-27

申请号：US13166144

申请日：2011-06-22

申请人： Cheng-Hsien Cheng ,  Wen-Jer Tsai ,  Shih-Guei Yan ,  Chih-Chieh Cheng ,  Jyun-Siang Huang

发明人： Cheng-Hsien Cheng ,  Wen-Jer Tsai ,  Shih-Guei Yan ,  Chih-Chieh Cheng ,  Jyun-Siang Huang

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/7887 ,  H01L21/28273 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/792 ,  H01L29/7923

摘要： A memory structure including a memory cell is provided, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. At least one of the first charge storage structure and the second charge storage structure includes two charge storage units which are physically separated. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source and drain and a second source and drain are disposed on the first dielectric layer and located at two sides of the channel layer.

摘要翻译： 提供包括存储单元的存储器结构，并且存储单元包括以下元件。 第一栅极设置在基板上。 层叠结构包括第一电介质结构，沟道层，第二电介质结构和设置在第一栅极上的第二栅极，设置在第一介电结构中的第一电荷存储结构和设置在第二电介质结构中的第二电荷存储结构 。 第一电荷存储结构和第二电荷存储结构中的至少一个包括物理分离的两个电荷存储单元。 第一电介质层在堆叠结构的两侧设置在第一栅极上。 第一源极和漏极以及第二源极和漏极设置在第一介电层上并位于沟道层的两侧。

公开(公告)号：US08143665B2

公开(公告)日：2012-03-27

申请号：US12352947

申请日：2009-01-13

申请人： Jyun-Siang Huang ,  Wen-Jer Tsai ,  Tien-Fan Ou

发明人： Jyun-Siang Huang ,  Wen-Jer Tsai ,  Tien-Fan Ou

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/11565 ,  H01L29/4234 ,  H01L29/792

摘要： The invention provides a memory array. The memory array comprises a substrate, a plurality of word lines, a charge trapping structure, a plurality of trench channels and a plurality of bit lines. The word lines are located over the substrate and the word lines are parallel to each other. The charge trapping structure covers a surface of each of the word lines. The trench channels are located over the substrate and the word lines and the trench channels are alternatively arranged and each trench channel is separated from the adjacent word lines by the charge trapping structure. The bit lines are located over the word lines and each bit line is across over each of the word lines and each trench channel is electrically coupled to the bit lines.

摘要翻译： 本发明提供一种存储器阵列。 存储器阵列包括衬底，多个字线，电荷俘获结构，多个沟槽沟道和多个位线。 字线位于衬底上，字线彼此平行。 电荷捕获结构覆盖每条字线的表面。 沟槽沟槽位于衬底之上，并且字线和沟槽沟槽交替布置，并且通过电荷捕获结构将每个沟槽沟道与相邻字线分开。 位线位于字线之上，并且每个位线跨越每一个字线，并且每个沟道沟道电耦合到位线。

公开(公告)号：US08139416B2

公开(公告)日：2012-03-20

申请号：US13159410

申请日：2011-06-13

申请人： Lit-Ho Chong ,  Wen-Jer Tsai ,  Tien-Fan Ou ,  Jyun-Siang Huang

发明人： Lit-Ho Chong ,  Wen-Jer Tsai ,  Tien-Fan Ou ,  Jyun-Siang Huang

IPC分类号： G11C11/34

CPC分类号： G11C5/04 ,  G11C16/0416 ,  G11C16/10 ,  H01L27/11521 ,  H01L27/11568

摘要： A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells.

摘要翻译： 一种用于对存储器阵列中的第一存储器单元进行编程的方法。 在具体实施例中，每个存储单元具有覆盖电荷存储材料和沟道的漏极，源极，沟道和控制栅极。 第一存储单元的源极耦合到第二存储单元的漏极。 电压施加到第一存储单元的漏极，并且第二存储单元的源极接地。 该方法包括使第二存储单元的漏极和第一存储单元的源极浮置，并且导通第一和第二存储单元的通道，从而有效地形成扩展通道区域。 将热载流子注入第一单元的电荷存储材料以对第一存储单元进行编程。 扩展通道降低电场，并减少未选择的存储单元中的冲击。