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    System and method for providing flexible signal routing and timing
    61.
    发明申请
    System and method for providing flexible signal routing and timing 有权
    提供灵活的信号路由和定时的系统和方法

    公开(公告)号：US20050267727A1

    公开(公告)日：2005-12-01

    申请号：US11140714

    申请日：2005-05-31

    Applicant: Mitchell Poplack ,  John Maher

    Inventor： Mitchell Poplack ,  John Maher

    IPC: G06F9/455

    CPC classification number: H04L43/50

    Abstract: A target interface system for flexibly routing and timing communication signals exchanged between selected components of a communication system and methods for manufacturing and using same. Under the control of a host system, the target interface system samples an output data signal provided by the host system and includes a reconfigurable datapath for flexibly routing the sampled data signal to a selected target I/O pin of the target interface system. The selected target I/O pin provides the sampled data signal as an outgoing target data signal to a target system and likewise receives an incoming target data signal from the target system. Upon sampling the incoming target data signal, the target interface system flexibly routes the sampled data signal to the host system as an input data signal. The target interface system thereby facilitates exchanges of communication signals between the host system and the target system.

    Abstract translation: 用于在通信系统的选定组件之间交换的灵活路由和定时通信信号的目标接口系统及其制造和使用方法。 在主机系统的控制下，目标接口系统对由主机系统提供的输出数据信号进行采样，并且包括用于将采样数据信号灵活地路由到目标接口系统的选定目标I / O引脚的可重构数据通路。 所选择的目标I / O引脚将采样的数据信号作为输出目标数据信号提供给目标系统，同样从目标系统接收输入的目标数据信号。 在对输入目标数据信号进行采样时，目标接口系统将采样的数据信号灵活地路由到主机系统作为输入数据信号。 因此，目标接口系统便于主机系统和目标系统之间的通信信号的交换。

    Clustered processors in an emulation engine
    62.
    发明申请
    Clustered processors in an emulation engine 有权
    集群处理器在仿真引擎中

    公开(公告)号：US20030212539A1

    公开(公告)日：2003-11-13

    申请号：US10459340

    申请日：2003-06-11

    Applicant: Quickturn Design Systems, Inc.

    Inventor： William F. Beausoleil ,  Tak-Kwong Ng ,  Helmut Roth ,  Peter Tannenbaum ,  N. James Tomassetti

    IPC: G06F009/455

    CPC classification number: G06F17/5027

    Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of nullcascadenull connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.

    Abstract translation: 处理器集群作为仿真引擎互连，使得处理器共享输入和数据堆栈，并行地完成结果的设置和存储，但是一个评估单元的输出连接到下一个评估单元的输入。 一组“级联”连接提供对中间值的访问。 通过点击一个处理器的中间值，并将它们馈送到下一个处理器，可以实现显着的仿真加速。

    Timing resynthesis in a multi-clock emulation system
    63.
    发明申请
    Timing resynthesis in a multi-clock emulation system 有权
    多时钟仿真系统中的时序再合成

    公开(公告)号：US20030084414A1

    公开(公告)日：2003-05-01

    申请号：US10246788

    申请日：2002-09-17

    Applicant: Quickturn Design Systems, Inc.

    Inventor： Platon Beletsky

    IPC: G06F017/50

    CPC classification number: G06F17/5027 ,  G06F17/505 ,  G06F17/5054

    Abstract: A method for resynthesizing gated clocks in a clock cone of a logic design having more than one input clock where the logic design will be implemented in a hardware logic emulation system. By resynthesizing the gated clocks, timing in the circuit becomes predictable. In the method, predicting logic that predicts which edges of said at least two input clocks may cause a hold time violation on a gated clock is generated. Then, the outputs from the predicting logic are connected to a gated clock resolution circuit, which outputs the resynthesized clock.

    Abstract translation: 一种用于在具有多于一个输入时钟的逻辑设计的时钟锥中重新合成门控时钟的方法，其中逻辑设计将在硬件逻辑仿真系统中实现。 通过重新合成门控时钟，电路中的时序变得可预测。 在该方法中，产生预测所述至少两个输入时钟的哪些边缘的逻辑，可能导致门控时钟上的保持时间违规。 然后，来自预测逻辑的输出连接到门控时钟分辨率电路，其输出再合成时钟。

    Logic analysis subsystem in a time-sliced emulator
    65.
    发明授权
    Logic analysis subsystem in a time-sliced emulator 失效
    时分片仿真器中的逻辑分析子系统

    公开(公告)号：US6141636A

    公开(公告)日：2000-10-31

    申请号：US831501

    申请日：1997-03-31

    Applicant: Tony R. Sarno ,  Ingo Schaefer ,  John E. Chilton ,  Mark S. Papamarcos ,  Bernard Y. Chan ,  Michael C. Tsou

    Inventor： Tony R. Sarno ,  Ingo Schaefer ,  John E. Chilton ,  Mark S. Papamarcos ,  Bernard Y. Chan ,  Michael C. Tsou

    IPC: G06F17/50 ,  G06F11/25 ,  G06F11/26 ,  G06F11/34 ,  G06F9/455

    CPC classification number: G06F11/261 ,  G06F11/25 ,  G06F11/3466

    Abstract: A logic analysis subsystem in a time-sliced emulator. The logic analysis subsystem "reconstructs" signals that were previously reduced by the compiler and allows the user to set breakpoints and triggers using these and other signals of the emulated circuit. The present invention includes a "logic analysis subsystem compiler" and "logic analysis subsystem hardware." The logic analysis subsystem compiler is either a subpart of the regular emulator compiler or is a standalone compiler. It compiles the design to be emulated and generates control instructions for the logic analysis subsystem hardware. The logic analysis subsystem hardware is incorporated into the time-sliced emulator to receive signals generated by the emulator during emulation. When the logic analysis subsystem operates, the control instructions cause the logic analysis subsystem to reconstruct previously reduced signals received from the emulator. These signals (along with the signals received from the emulator) may be used by the user to set breakpoints and triggers in the logic analysis subsystem.

    Abstract translation: 时间分片仿真器中的逻辑分析子系统。 逻辑分析子系统“重建”先前由编译器减少的信号，并允许用户使用仿真电路的这些和其他信号来设置断点和触发。 本发明包括“逻辑分析子系统编译器”和“逻辑分析子系统硬件”。 逻辑分析子系统编译器是常规仿真器编译器的子部分，也可以是独立编译器。 它编译要仿真的设计，并为逻辑分析子系统硬件生成控制指令。 逻辑分析子系统硬件被并入到时间分割的仿真器中，以在仿真期间接收由仿真器产生的信号。 当逻辑分析子系统运行时，控制指令使逻辑分析子系统重建从仿真器接收的先前减小的信号。 这些信号（以及从仿真器接收到的信号）可以由用户用于在逻辑分析子系统中设置断点和触发器。

    Latch optimization in hardware logic emulation systems
    67.
    发明授权
    Latch optimization in hardware logic emulation systems 失效
    硬件逻辑仿真系统中的锁存优化

    公开(公告)号：US5886904A

    公开(公告)日：1999-03-23

    申请号：US718655

    申请日：1996-09-23

    Applicant: Wei-Jin Dai ,  Junjing Yan

    Inventor： Wei-Jin Dai ,  Junjing Yan

    IPC: G06F17/50 ,  G06F9/455

    CPC classification number: G06F17/5045 ,  G06F17/5027

    Abstract: A method for optimizing a logical design for emulation. The present invention optimzes latch-based designs by transforming them into a flip-flop based circuit. The design is analyzed to determine whether any consecutive latches are clocked by the same clock signal. If consecutive latches are clocked by the same clock signal, for example, the same phase of the same master clock, a transparency condition exists. Transparent latches are transformed into either a flip-flop/buffer/multiplexer circuit or a buffer circuit depending upon whether the latch in the logic design has an enable input. If consecutive latches in a design are clocked by different clock signals, i.e., different phases of the master clock, no transparency condition exists. Non-transparent latches are transformed into a flip-flop.

    Abstract translation: 一种优化仿真逻辑设计的方法。 本发明通过将基于锁存器的设计转换为基于触发器的电路来优化基于锁存器的设计。 分析设计以确定是否有任何连续锁存器由相同的时钟信号计时。 如果连续锁存器由相同的时钟信号计时，例如同一个主时钟的同相，则存在透明度条件。 根据逻辑设计中的锁存器是否具有使能输入，透明锁存器被转换成触发器/缓冲器/多路复用器电路或缓冲器电路。 如果设计中的连续锁存器由不同的时钟信号（即主时钟的不同相位）计时，则不存在透明度条件。 非透明锁存器被转换成触发器。

    Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation
    68.
    发明授权
    Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation 失效
    将激励和响应函数添加到正在进行仿真的电路设计中的结构和方法

    公开(公告)号：US5661662A

    公开(公告)日：1997-08-26

    申请号：US471679

    申请日：1995-06-06

    Applicant: Michael R. Butts ,  Jon A. Batcheller

    Inventor： Michael R. Butts ,  Jon A. Batcheller

    IPC: G06F17/50 ,  H03K17/693 ,  H03K17/735

    CPC classification number: G06F17/5027 ,  G06F17/5054 ,  G06F17/5068

    Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

    Abstract translation: 多个电子可重构门阵列（ERCGA）逻辑芯片经由可重配置互连互连，并且大数字网络的电子表示被转换为在互连芯片上采取暂时的实际操作硬件形式。 可重构互连允许在互连芯片上实现的数字网络随意改变，使系统非常适合于各种目的，包括仿真，原型设计，执行和计算。 可重配置互连可以包括由专用于互连功能的ERCGA芯片形成的部分交叉开关，其中每个这样的互连ERCGA连接到多个逻辑芯片的至少一个但不是全部的引脚。 其他可重配置互连拓扑也是详细的。

    Hierarchically connected reconfigurable logic assembly
    70.
    发明授权
    Hierarchically connected reconfigurable logic assembly 失效
    层次连接的可重构逻辑组件

    公开(公告)号：US5452231A

    公开(公告)日：1995-09-19

    申请号：US245310

    申请日：1994-05-17

    Applicant: Michael R. Butts ,  Jon A. Batcheller

    Inventor： Michael R. Butts ,  Jon A. Batcheller

    IPC: G06F17/50 ,  H03K17/693 ,  H03K17/735

    CPC classification number: G06F17/5027 ,  G06F17/5054 ,  G06F17/5068

    Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic circuits are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected circuits. The reconfigurable interconnect permits the digital network realized on the interconnected circuits to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA circuits dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic circuits. Other reconfigurable interconnect topologies are also detailed. If desired, the logic circuits and interconnect can be implemented in wafer-scale technology. Hybrid simulation employing both an ERCGA hardware simulator and a second simulator permits intermediate states of a circuit's operation to be reached quickly and analyzed in detail.

    Abstract translation: 多个电子可重构门阵列（ERCGA）逻辑电路经由可重配置互连互连，并且大数字网络的电子表示被转换为在互连电路上采取暂时的实际操作硬件形式。 可重构互连允许在互连电路上实现的数字网络随意改变，使得该系统非常适合于各种目的，包括仿真，原型设计，执行和计算。 可重构互连可以包括由专用于互连功能的ERCGA电路形成的部分交叉开关，其中每个这样的互连ERCGA连接到多个逻辑电路中的至少一个但不是全部的引脚。 其他可重配置互连拓扑也是详细的。 如果需要，逻辑电路和互连可以在晶片级技术中实现。 使用ERCGA硬件模拟器和第二模拟器的混合仿真器允许快速到达电路的操作的中间状态并且进行详细分析。

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