公开(公告)号：US06966018B2

公开(公告)日：2005-11-15

申请号：US09870955

申请日：2001-05-30

申请人： Klaus-Dieter Hilliges

发明人： Klaus-Dieter Hilliges

IPC分类号： G01R31/28 ,  G01R31/319 ,  G06F11/22

CPC分类号： G01R31/31907 ,  G01R31/31908 ,  G01R31/31926

摘要： Automated test equipment (ATE) includes a tester-per-pin architecture with a number of individual decentralized per-pin testing units, wherein each per-pin testing unit is adapted for testing a respective DUT-pin of a device under test (DUT) by emitting stimulus response signals to the respective DUT-pin and/or receiving stimulus response signals from the respective DUT-pin. Testing the DUT includes defining for a testing sequence the DUT into one or more DUT-cores representing one or more functional units of the DUT and covering one or more DUT-pins of the DUT, and assigning during the testing sequence one or more of the per-pin testing units to one or more ATE-ports, whereby each ATE-port comprises one or more of the per-pin testing units and represents an independent functional testing unit for testing one or more of the DUT-cores during the testing sequence.

摘要翻译： 自动测试设备（ATE）包括一个具有多个独立分散式每针测试单元的每针脚架构测试单元，其中每个针脚测试单元适用于测试待测器件（DUT）的相应DUT引脚， 通过向相应的DUT引脚发射刺激响应信号和/或从相应的DUT引脚接收刺激响应信号。 测试DUT包括将DUT的测试序列定义为表示DUT的一个或多个功能单元的一个或多个DUT核并且覆盖DUT的一个或多个DUT引脚，并且在测试序列期间分配一个或多个 每个引脚测试单元连接到一个或多个ATE端口，由此每个ATE端口包括一个或多个每引脚测试单元，并且表示用于在测试序列期间测试一个或多个DUT核的独立功能测试单元 。

公开(公告)号：US20050248374A1

公开(公告)日：2005-11-10

申请号：US10842746

申请日：2004-05-10

申请人： Eric Kushnick

发明人： Eric Kushnick

IPC分类号： G01R31/28 ,  G01R31/319 ,  G06F1/03 ,  H03B21/02

CPC分类号： G06F1/0328 ,  G01R31/31907 ,  G01R31/31917 ,  G06F2101/04

摘要： The present invention is directed to the use of a DDS to generate a high purity reference signal with high frequency resolution by switching a frequency tuning word (FTW) between particular values for particular time durations to produce two or more closely spaced frequencies that appear at the DDS output as a single frequency. Given a DDS switching between F1 and F2 such that F1 is present for time T1 and F2 is present for time T2, with the total period of the repeating pattern being T=T1+T2, in order for the output of the DDS to produce a single high-purity frequency that is the time-weighted average of the alternating frequencies, the condition |F1−F2|

摘要翻译： 本发明涉及使用DDS通过在特定时间间隔内的特定值之间切换频率调谐字（FTW）来产生具有高频分辨率的高纯度参考信号，以产生两 DDS输出为单频。 给定F1和F2之间的DDS切换，使得F1存在时间T1，F2存在于时间T2，重复模式的总周期为T = T1 + T2，以便DDS的输出产生 单个高纯度频率是交变频率的时间加权平均值，条件| F1-F2 | << pi / T必须满足。 时间加权平均频率Favg =（T1.F1 + T2.F2）/（T + T2）。 通过适当选择T1和T2，Favg可以设置为这两个频率之间的任何频率。

公开(公告)号：US20050209809A1

公开(公告)日：2005-09-22

申请号：US11076734

申请日：2005-03-10

申请人： Takuya Otani

发明人： Takuya Otani

IPC分类号： G01R31/28 ,  G01R31/319 ,  G08C19/00 ,  H04L12/24 ,  H04Q9/00 ,  G06F19/00

CPC分类号： G01R31/31907 ,  G01R31/2834

摘要： A measurement system comprising modules for receiving analog measurement signals and outputting digital data and a controller for receiving and data processing of these digital data, this measurement system, wherein these modules comprise a A/D converter for converting analog measurement signals to digital data and measuring these data, an output for outputting these digital data, and a controller for controlling the timing of these measurements and the timing of these outputs, and in that the control by the controller is accomplished by outputting during the breaks between multiple measurements.

摘要翻译： 一种测量系统，包括用于接收模拟测量信号并输出​​数字数据的模块以及用于接收和数据处理这些数字数据的控制器，该测量系统包括用于将模拟测量信号转换为数字数据并测量的A / D转换器 这些数据，用于输出这些数字数据的输出，以及用于控制这些测量的定时和这些输出的定时的控制器，并且控制器的控制是通过在多个测量之间的断开期间输出来实现的。

公开(公告)号：US20050182588A1

公开(公告)日：2005-08-18

申请号：US10778463

申请日：2004-02-12

申请人： Gordon Chenoweth ,  Marc Loranger ,  Steven Payne ,  James Larson ,  Patricia Justice

发明人： Gordon Chenoweth ,  Marc Loranger ,  Steven Payne ,  James Larson ,  Patricia Justice

IPC分类号： G01R31/317 ,  G01R31/319 ,  G06F19/00

CPC分类号： G01R31/31907 ,  G01R31/31713

摘要： A system for testing an integrated circuit device under test (DUT) communicating though synchronous digital signals and through a high speed serialization/de-serialization (serdes) bus includes a serdes interface circuit for communicating with the DUT via the serdes bus and an integrated circuit (IC) tester for communicating with the DUT and with the serdes interface circuit via digital signals. State changes in the digital signals are synchronized to a clock signal within the IC tester. The serdes interface circuit receives instructions from the IC tester via at least one of the digital signals and responds to the instructions by transmitting data to the DUT via the serdes bus using appropriate serdes protocol, by receiving and storing data transmitted by the DUT via the serdes bus, and by thereafter forwarding the stored data to the IC tester via at least one of the digital signals.

摘要翻译： 一种用于测试通过同步数字信号进行通信的集成电路设备（DUT）和通过高速串行化/解串行化（serdes）总线）的系统，包括用于经由serdes总线和集成电路与DUT通信的serdes接口电路 （IC）测试仪，通过数字信号与DUT和serdes接口电路进行通信。 数字信号中的状态变化与IC测试仪内的时钟信号同步。 Serdes接口电路通过至少一个数字信号接收来自IC测试器的指令，并通过使用适当的serdes协议通过serdes总线将数据发送到DUT来响应指令，通过接收和存储由DUT通过serdes发送的数据 总线，然后通过至少一个数字信号将所存储的数据转发到IC测试器。

公开(公告)号：US20050102592A1

公开(公告)日：2005-05-12

申请号：US11021965

申请日：2004-12-21

申请人： Michael Jones ,  Frederic Giral ,  William Fritzsche

发明人： Michael Jones ,  Frederic Giral ,  William Fritzsche

IPC分类号： G01R31/319 ,  G01R31/28

CPC分类号： G01R31/31907 ,  G01R31/31922

摘要： Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.

公开(公告)号：US20050039079A1

公开(公告)日：2005-02-17

申请号：US10814603

申请日：2004-03-31

申请人： Shinsaku Higashi ,  Seiji Ichiyoshi ,  Ankan Pramanick ,  Mark Elston ,  Leon Chen ,  Robert Sauer ,  Ramachandran Krishnaswamy ,  Harsanjeet Singh ,  Toshiaki Adachi ,  Yoshihumi Tahara

发明人： Shinsaku Higashi ,  Seiji Ichiyoshi ,  Ankan Pramanick ,  Mark Elston ,  Leon Chen ,  Robert Sauer ,  Ramachandran Krishnaswamy ,  Harsanjeet Singh ,  Toshiaki Adachi ,  Yoshihumi Tahara

IPC分类号： G01R31/3183 ,  G01R31/319 ,  H02H3/05

CPC分类号： G01R31/3183 ,  G01R31/318307 ,  G01R31/318342 ,  G01R31/31907

摘要： There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of the test signal generating timings output by the timing alignment section to generate the test signal in simulation in the cycle time corresponding to the test signal generating timing.

摘要翻译： 提供了一种用于模拟测试装置的测试仿真器，该测试装置包括用于将测试信号分别提供给被测试器件的多个测试模块，包括：多个测试模块仿真部分，用于仿真基于不同的测试信号生成测试信号的多个测试模块 循环，用于仿真用于控制被测设备的测试的控制装置的控制仿真部分，用于产生测试信号产生定时的同步仿真部分，多个测试模块仿真部分中的每个测试信号产生定时部分将在其中生成测试信号 基于来自控制仿真部分的指令，对应于测试模块仿真部分的周期时间的模拟定时对准部分，用于对准由同步仿真部分按时间顺序产生的多个测试信号产生定时，并且通过 一个以及用于引起测试模块仿真部分的调度部分 对应于由定时对准部分输出的测试信号产生定时之一，以在对应于测试信号产生定时的周期时间中在仿真中产生测试信号。

公开(公告)号：US20040210798A1

公开(公告)日：2004-10-21

申请号：US10404002

申请日：2003-03-31

发明人： Shinsaku Higashi

IPC分类号： G06F009/455

CPC分类号： G01R31/318307 ,  G01R31/318342 ,  G01R31/31907

摘要： There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of the test signal generating timings output by the timing alignment section to generate the test signal in simulation in the cycle time corresponding to the test signal generating timing.

摘要翻译： 提供了一种用于模拟测试装置的测试仿真器，该测试装置包括用于将测试信号分别提供给被测试器件的多个测试模块，包括：多个测试模块仿真部分，用于仿真基于不同的测试信号生成测试信号的多个测试模块 循环，用于仿真用于控制被测设备的测试的控制装置的控制仿真部分，用于产生测试信号产生定时的同步仿真部分，多个测试模块仿真部分中的每个测试信号产生定时部分将生成测试信号， 基于来自控制仿真部分的指令，对应于测试模块仿真部分的周期时间的模拟定时对准部分，用于对准由同步仿真部分按时间顺序产生的多个测试信号产生定时，并且通过 一个以及用于引起测试模块仿真部分的调度部分 对应于由定时对准部分输出的测试信号产生定时之一，以在对应于测试信号产生定时的周期时间中在仿真中产生测试信号。

公开(公告)号：US20040201077A1

公开(公告)日：2004-10-14

申请号：US10829320

申请日：2004-04-21

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Tomomi Momohara

IPC分类号： H03K019/0175

CPC分类号： G11C29/48 ,  G01R31/31721 ,  G01R31/318505 ,  G01R31/318511 ,  G01R31/31907 ,  G01R31/31924 ,  G01R31/31926 ,  G11C5/025 ,  G11C29/006 ,  G11C29/08 ,  G11C29/12005 ,  G11C29/56 ,  G11C2029/0401 ,  G11C2029/5002 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes a semiconductor substrate of a first conductive type, a first well of a second conductive type provided in the semiconductor substrate, a second well of the first conductive type provided in the first well, a third well of the second conductive type provided in the semiconductor substrate, a fourth well of the first conductive type provided in the third well, semiconductor elements constructing a first functional integrated circuit provided in the first and second wells, semiconductor elements constructing a second functional integrated circuit provided in the third and fourth wells, and an internal Power source voltage generating circuit provided in the first well. The internal power source voltage generating circuit configured to generate a first internal power source voltage is applied to the first functional integrated circuit and a second internal power source voltage is applied to the second functional integrated circuit.

摘要翻译： 半导体集成电路器件包括第一导电类型的半导体衬底，设置在半导体衬底中的第二导电类型的第一阱，设置在第一阱中的第一导电类型的第二阱，第二导电类型的第三阱 设置在第三阱中的第一导电类型的第四阱，构成第一和第二阱中的第一功能集成电路的半导体元件，构成在第三阱中提供的第二功能集成电路的半导体元件和 第四井和设置在第一井中的内部电源电压产生电路。 配置为产生第一内部电源电压的内部电源电压产生电路被施加到第一功能集成电路，并且第二内部电源电压被施加到第二功能集成电路。

公开(公告)号：US06779140B2

公开(公告)日：2004-08-17

申请号：US09896474

申请日：2001-06-29

申请人： Alan S Krech, Jr. ,  Edmundo De La Puente ,  Joel Buck-Gengler

发明人： Alan S Krech, Jr. ,  Edmundo De La Puente ,  Joel Buck-Gengler

IPC分类号： G11C2900

CPC分类号： G11C29/56 ,  G01R31/31907

摘要： A Test Station for a memory tester is comprised of one or more Test Sites that are each individually algorithmically controllable, that can each deal with as many as sixty-four channels, and that can be bonded together to form a Multi-Site Test Station of two or more Test Sites. Up to nine Test Sites can be bonded together as a single Multi-Site Test Station. Bonded Test Sites still operate at the highest speeds they were capable of when not bonded. To bring this about it is necessary to implement certain programming conventions and to provide certain housekeeping functions relating to simultaneous starting of separate test programs on the bonded Test Sites, and relating to propagation and synchronization of test program qualifier results among those separate test programs. There also is a suspend/resume test program execution mechanism that assists one test program in temporarily interrupting the others to allow time for a change within one or more of the Test Sites of a measurement parameter, such as a voltage comparison threshold.

摘要翻译： 用于记忆测试仪的测试站由一个或多个测试站组成，每个测试站点各自具有算术可控性，每个测试站点可以处理多达六十四个通道，并且可以结合在一起以形成多站点测试站 两个或多个测试站点。 多达9个测试站点可以作为单个多站点测试站绑定在一起。 保税测试站点仍然以最高的速度运行，当他们没有绑定时能够实现。 为了实现这一点，有必要实施某些编程约定，并提供与在绑定的测试站点上单独测试程序同时启动有关的某些内务管理功能，以及与单独的测试程序之间的测试程序限定符结果的传播和同步有关。 还有一个暂停/恢复测试程序执行机制，协助一个测试程序临时中断其他测试程序，以便在测量参数的一个或多个测试站点内进行更改，例如电压比较阈值。

公开(公告)号：US20040068685A1

公开(公告)日：2004-04-08

申请号：US10335384

申请日：2002-12-30

发明人： Ming Huan Yuan ,  Chia Yuan Liu

IPC分类号： G01R031/317

CPC分类号： G01R31/318342 ,  G01R31/31907 ,  G01R31/31926

摘要： A simulation system for testing IDE channels includes a testing board (100), a tested board electrically connected to the testing board and having at least an IDE chip with IDE channels to be tested, and a firmware having testing programs embedded therein. The firmware is electrically connected to the tested board in advance. The testing board has an IDE interface (101) for electrically connecting with the tested board, a buffer (102) for storing data temporarily, and a decoder (103) for decoding IDE commands. A simulation method for testing IDE channels includes acts of providing the above-mentioned components and executing the testing programs embedded in the firmware.

摘要翻译： 用于测试IDE通道的模拟系统包括测试板（100），电连接到测试板并具有至少一个具有要测试的IDE通道的IDE芯片的测试板以及嵌入其中的测试程序的固件。 固件预先与测试板电连接。 测试板具有用于与测试板电连接的IDE接口（101），用于临时存储数据的缓冲器（102）和用于解码IDE命令的解码器（103）。 用于测试IDE通道的模拟方法包括提供上述组件并执行嵌入在固件中的测试程序的动作。