公开(公告)号：US20110050414A1

公开(公告)日：2011-03-03

申请号：US12553806

申请日：2009-09-03

申请人： Nikolai Vyssotski ,  Richard Tonry

发明人： Nikolai Vyssotski ,  Richard Tonry

IPC分类号： G08B21/00

CPC分类号： G06K1/00 ,  G06F1/22 ,  H01L21/00

摘要： Systems and methods for detecting states are disclosed. An information handling system may include a processor and a plurality of information handling resources communicatively coupled to the processor via the common control line. The processor may be configured to produce a first signal on a common control line. Each of the plurality of information handling resources may include a tag having a signal threshold, the tag configured to communicate a second signal via the common control line indicating the presence of the particular information handling resource in response to the first signal exceeding the signal threshold of the tag.

摘要翻译： 公开了用于检测状态的系统和方法。 信息处理系统可以包括经由公共控制线路通信地耦合到处理器的处理器和多个信息处理资源。 处理器可以被配置为在公共控制线上产生第一信号。 多个信息处理资源中的每一个可以包括具有信号阈值的标签，所述标签被配置为响应于超过第一信号的信号阈值而经由公共控制线路传送指示特定信息处理资源的存在的第二信号 标签。

公开(公告)号：US07881813B2

公开(公告)日：2011-02-01

申请号：US11424767

申请日：2006-06-16

申请人： James M. Sibigtroth ,  Dionicio Garcia, III

发明人： James M. Sibigtroth ,  Dionicio Garcia, III

IPC分类号： G05B11/01 ,  G01R31/28

CPC分类号： G06F1/22 ,  G06F1/24 ,  G06F11/27

摘要： Methods and data processing systems are provided to share a common pin between two circuits in microcontroller unit (MCU). Signals are received at a common pin included in the MCU. If the first circuit has been enabled, then the received signals are analyzed to determine whether the signals are valid command signals for the first circuit. If the signals are not a valid command signal, then a second circuit is performed. If the first circuit has not been enabled, then an alternate function is performed. One of the operations performed by the alternate function is to determine whether to enable the first function. In one embodiment, the first circuit is a background debug controller of the MCU and the second circuit is a reset circuit.

摘要翻译： 提供了方法和数据处理系统，以在微控制器单元（MCU）中的两个电路之间共享公共引脚。 在MCU中包含的公共引脚上接收到信号。 如果第一电路已被使能，则分析接收的信号以确定信号是否是用于第一电路的有效命令信号。 如果信号不是有效的命令信号，则执行第二电路。 如果第一个电路尚未使能，则执行一个备用功能。 交替功能执行的操作之一是确定是否启用第一个功能。 在一个实施例中，第一电路是MCU的背景调试控制器，第二电路是复位电路。

公开(公告)号：US20100299473A1

公开(公告)日：2010-11-25

申请号：US12851156

申请日：2010-08-05

申请人： Yu-Lan Kuo ,  Chun-Hsiung Hung

发明人： Yu-Lan Kuo ,  Chun-Hsiung Hung

IPC分类号： G06F13/14

CPC分类号： G06F13/4291 ,  G06F1/22 ,  G06F13/385 ,  G06F13/40 ,  G06F13/4022 ,  G06F13/404

摘要： A serial peripheral interface of an integrated circuit including multiple pins and a clock pin is provided. The pins are coupled to the integrated circuit for transmitting an instruction, an address or a read out data. The clock pin is coupled to the integrated circuit for inputting multiple timing pulses. The plurality of pins transmit the instruction, the address or the read out data at rising edges, falling edges or both edges of the timing pulses.

摘要翻译： 提供了包括多个引脚和时钟引脚的集成电路的串行外设接口。 引脚耦合到集成电路，用于发送指令，地址或读出数据。 时钟引脚耦合到集成电路，用于输入多个定时脉冲。 多个引脚在定时脉冲的上升沿，下降沿或两个边缘发送指令，地址或读出数据。

公开(公告)号：US07840900B1

公开(公告)日：2010-11-23

申请号：US12433499

申请日：2009-04-30

申请人： Stephan Rosner ,  Qamrul Hasan ,  Roger Dwain Isaac

发明人： Stephan Rosner ,  Qamrul Hasan ,  Roger Dwain Isaac

IPC分类号： G06F15/00 ,  G06F13/00

CPC分类号： G06F1/24 ,  G06F1/22 ,  G06F11/0757

摘要： Systems and methods are disclosed that replace a separate reset pin in a bus with a reset command that guarantees a system recovery. The system comprises a host component circuitry residing on a first chip and a client component circuitry residing on a second, different chip. A bus connects the host component circuitry to the client component circuitry. The host component circuitry is configured to transfer an initial client value associated with a client component time period to the client component circuitry over the bus on a periodic time basis. The periodic time basis is dictated by a host component time period and the client component time period is greater than the host component time period. The client component circuitry is configured to initiate a reset procedure if the client component time period expires which indicates that the initial client value was not received at a next time on the periodic time basis dictated by the host component time period.

摘要翻译： 公开了一种系统和方法，用一个复位命令来代替总线中的一个单独的复位引脚，保证系统恢复。 该系统包括驻留在第一芯片上的主机组件电路和驻留在第二不同芯片上的客户端组件电路。 总线将主机组件电路连接到客户端组件电路。 主机组件电路被配置为以周期性的时间通过总线将与客户端组件时间段相关联的初始客户端值传送到客户端组件电路。 周期时间基准由主机组件时间段指定，并且客户端组件时间段大于主机组件时间段。 如果客户端组件时间段到期，则客户端组件电路被配置为启动重置过程，其指示在由主机组件时间段指定的周期时间基础上的下一次未接收到初始客户端值。

公开(公告)号：US07822076B2

公开(公告)日：2010-10-26

申请号：US12070271

申请日：2008-02-15

申请人： Douglas A. Larson

发明人： Douglas A. Larson

IPC分类号： H04J99/00

CPC分类号： H03K19/1732 ,  G06F1/10 ,  G06F1/22 ,  G06F13/4022 ,  G06F13/4072

摘要： One embodiment of the present invention provides an apparatus that selectively multiplexes a plurality of signal lines through an I/O pin on a semiconductor chip. This apparatus includes an I/O pin, for coupling a signal line within the semiconductor chip to a signal line outside of the semiconductor chip. A transmitting circuit is configured to selectively multiplex the plurality of signal lines onto the I/O pin. A receiving circuit is configured to receive multiplexed data from the I/O pin, and to reverse the multiplexing so that values originally from the multiplexed signal lines are separated into distinct signals in the receiving circuit. Note that the transmitting circuit and the receiving circuit are driven by a common clock signal. The apparatus additionally includes an initialization circuit that selectively configures the transmitting circuit and the receiving circuit to multiplex at least one of the plurality of signal lines through the I/O pin.

摘要翻译： 本发明的一个实施例提供了一种通过半导体芯片上的I / O引脚选择性地复用多条信号线的装置。 该装置包括用于将半导体芯片内的信号线耦合到半导体芯片外部的信号线的I / O引脚。 发送电路被配置为将多个信号线选择性地复用到I / O引脚上。 接收电路被配置为从I / O引脚接收多路复用数据，并且反转多路复用，使得最初来自多路复用信号线的值在接收电路中被分离成不同的信号。 注意，发射电路和接收电路由公共时钟信号驱动。 该装置还包括初始化电路，其选择性地配置发送电路和接收电路以通过I / O引脚复用多条信号线中的至少一条信号线。

公开(公告)号：US20100164538A1

公开(公告)日：2010-07-01

申请号：US12085557

申请日：2006-11-16

申请人： Bernhard Greimel-Rechling

发明人： Bernhard Greimel-Rechling

IPC分类号： H03K19/003

CPC分类号： G06F1/22 ,  H03K19/1732

摘要： An input circuit arrangement (1) comprises an input (2), a comparator (30), and an evaluation circuit (50). The input (2) is designed for coupling to a first terminal (101) of an impedance (100) and for feeding an input signal (ES). The comparator (30) is connected to the input (2) of the input circuit arrangement (1) and is designed for delivering an activation signal (S1) to an output (31) as a function of a comparison of the input signal (ES) with an adjustable threshold (SW1). Furthermore, the evaluation circuit (50) is connected to the input (2) of the input circuit arrangement (1) and for its activation to the output (31) of the comparator (30) and is designed for evaluating the value of the impedance (100) that can be connected.

摘要翻译： 输入电路装置（1）包括输入（2），比较器（30）和评估电路（50）。 输入（2）被设计用于耦合到阻抗（100）的第一端子（101）并且用于馈送输入信号（ES）。 比较器（30）连接到输入电路装置（1）的输入端（2），被设计成根据输入信号（ES）的比较将激活信号（S1）输出到输出端 ）具有可调阈值（SW1）。 此外，评估电路（50）连接到输入电路装置（1）的输入端（2）并将其激活到比较器（30）的输出端（31），并被设计用于评估阻抗值 （100）可以连接。

公开(公告)号：US20100103185A1

公开(公告)日：2010-04-29

申请号：US12582171

申请日：2009-10-20

申请人： Donald Pannell

发明人： Donald Pannell

IPC分类号： G09G5/36 ,  G11C5/02 ,  G11C7/00

CPC分类号： H03K19/1732 ,  G06F1/22 ,  H05B33/0806

摘要： An integrated circuit (IC) within an IC package, where the IC includes a memory control module and a timing module. The memory control module is configured to control read/write operations of a memory IC via N pins of the IC package, where N is an integer greater than 1. The memory IC is external to the IC package. The timing module is configured to control on/off timing of (N*M) light emitting diodes (LEDs) arranged in N columns and M rows connected to the N pins and M pins of the IC, respectively, where M is an integer greater than 1. The read/write operations utilize the N pins during a first period. The N*M LEDs receive data from the M pins and refresh signals from the N pins during a second period that is different than the first period.

摘要翻译： IC封装内的集成电路（IC），其中IC包括存储器控制模块和定时模块。 存储器控制模块被配置为通过IC封装的N个引脚来控制存储器IC的读/写操作，其中N是大于1的整数。存储器IC在IC封装的外部。 定时模块被配置为控制分别连接到IC的N个引脚和M个引脚的N列和M行中布置的（N * M）个发光二极管（LED）的接通/断开定时，其中M是更大的整数 读/写操作在第一个周期期间利用N个引脚。 N * M LED在与第一个周期不同的第二个周期内从M个引脚接收数据并从N个引脚刷新信号。

公开(公告)号：US20090210566A1

公开(公告)日：2009-08-20

申请号：US12032990

申请日：2008-02-18

申请人： Robert Christopher Dixon ,  John Wayne Hartfiel ,  Hien Minh Le ,  Tung Nguyen Pham

发明人： Robert Christopher Dixon ,  John Wayne Hartfiel ,  Hien Minh Le ,  Tung Nguyen Pham

IPC分类号： G06F3/00

CPC分类号： G06F1/22 ,  G01R31/318572 ,  G06F11/006 ,  G06F11/2236

摘要： The present invention provides for a system. The system includes a plurality of controllers, each controller comprising at least an output pin and a plurality of input pins and configured to receive self-identify control signals through one or more of the plurality of input pins and to transmit a controller self-identify signal through the output pin based on the self-identify control signals. Each output pin is coupled to an external system. A processor couples to a first input pin of the plurality of input pins of each of the plurality of controllers and is configured to generate self-identify control signals and to transmit the self-identify control signals to the plurality of controllers.

摘要翻译： 本发明提供一种系统。 该系统包括多个控制器，每个控制器包括至少一个输出引脚和多个输入引脚，并且被配置为通过多个输入引脚中的一个或多个接收自识别控制信号，并且发送控制器自识别信号 通过输出引脚基于自识别控制信号。 每个输出引脚耦合到外部系统。 处理器耦合到多个控制器中的每一个的多个输入引脚中的第一输入引脚，并被配置为产生自识别控制信号并将自识别控制信号发送到多个控制器。

公开(公告)号：US20090153211A1

公开(公告)日：2009-06-18

申请号：US12002711

申请日：2007-12-17

申请人： Neil Hendin ,  Zahid Najam ,  Stephane Le Provost ,  Brian Smith

发明人： Neil Hendin ,  Zahid Najam ,  Stephane Le Provost ,  Brian Smith

IPC分类号： H03K3/02

CPC分类号： G06F1/22 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D50/20

摘要： In an integrated circuit device, a circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The circuit includes an interface for coupling a functional block of a processor to an input and output pin and an output storage element coupled to the interface for storing a current value of the input output pin. The circuit further includes a sleep mode enable for controlling the output storage element to store the current value of the input output pin prior to the functional block being entering a sleep mode and cause the current value of the input output pin to remain asserted after the functional block is in sleep mode. The sleep mode enable is also to deactivate the storage element when the sleep mode is exited.

摘要翻译： 在集成电路器件中，当器件的功能块处于休眠模式时，用于在器件的输入输出引脚上维持有效值的电路。 该电路包括用于将处理器的功能块耦合到输入和输出引脚的接口和耦合到接口的输出存储元件，用于存储输入输出引脚的当前值。 电路还包括睡眠模式使能，用于在功能块进入休眠模式之前控制输出存储元件以存储输入输出引脚的当前值，并且使得输入输出引脚的当前值在功能块之后保持断言 块处于睡眠模式。 睡眠模式启用也是在休眠模式退出时停用存储元件。

公开(公告)号：US07392954B2

公开(公告)日：2008-07-01

申请号：US11530766

申请日：2006-09-11

申请人： Taojin Li ,  Shanquan Bao ,  Jie Sun ,  Xin Liu

发明人： Taojin Li ,  Shanquan Bao ,  Jie Sun ,  Xin Liu

IPC分类号： G06K19/06

CPC分类号： G06F1/22 ,  G06F13/4291

摘要： A reduced pin count connection system for an insertable operational systems card having a plurality of input and output signals to a host device having operational circuits responsive to the input and output signals of the card includes a master serial data link in the card for communicating at least a portion of the plurality of input and output signals of the card. A slave serial data link is operably interconnected to the master serial data link through a connector having a second plurality contacts less than the plurality of input and output signals and communicates the input and output signals to the operational circuits in the host device.

摘要翻译： 一种用于可插入操作系统卡的减少的针数连接系统，其具有多个输入和输出信号到具有响应于卡的输入和输出信号的操作电路的主机设备，包括用于至少通信的卡中的主串行数据链路 卡的多个输入和输出信号的一部分。 从串行数据链路通过具有小于多个输入和输出信号的第二多个触点的连接器可操作地连接到主串行数据链路，并将输入和输出信号传送到主机设备中的操作电路。