公开(公告)号：US08754599B2

公开(公告)日：2014-06-17

申请号：US13790719

申请日：2013-03-08

申请人： Fanuc Corporation

发明人： Taku Sasaki ,  Yasusuke Iwashita

IPC分类号： H02P6/16

CPC分类号： H02P23/00 ,  H03M3/494

摘要： A motor control apparatus includes a power conversion unit which supplies drive power to a motor, a current detection unit which detects the value of a current flowing from the power conversion unit to the motor, a delta-sigma modulation AD converter to which the current value detected by the current detection unit is input as analog data, and which includes a modulator and a plurality of digital low-pass filters and outputs digital data in accordance with the filter characteristics of the respective digital low-pass filters, and a command generating unit which is connected to the digital low-pass filter to be used for motor drive control among the plurality of digital low-pass filters, and which generates a drive command to the power conversion unit by using the digital data output from the motor drive controlling digital low-pass filter.

摘要翻译： 电动机控制装置包括向电动机提供驱动电力的电力转换单元，检测从电力转换单元流向电动机的电流的值的电流检测单元，电流值的Δ-Σ调制AD转换器 由电流检测单元检测的信号作为模拟数据输入，并且包括调制器和多个数字低通滤波器，并且根据各个数字低通滤波器的滤波特性输出数字数据，以及指令生成单元 其连接到数字低通滤波器，用于多个数字低通滤波器之间的电动机驱动控制，并且通过使用从电动机驱动器输出的数字数据产生驱动命令，控制数字 低通滤波器。

公开(公告)号：US07948270B1

公开(公告)日：2011-05-24

申请号：US12648756

申请日：2009-12-29

申请人： William Pierce Evans ,  Adrian Leuciuc

发明人： William Pierce Evans ,  Adrian Leuciuc

IPC分类号： H03K19/0175 ,  H03K5/00 ,  G06F7/38

CPC分类号： H03K5/003 ,  H03K5/2481 ,  H03K5/249 ,  H03M3/494

摘要： The serial interface operable, for example, to facilitate high speed differential data transfer between integrated circuits provides level shifting of an incoming data signal using a switched capacitor technique which level shifts the common mode voltage with minimal attenuation and minimal reduction of bandwidths. The serial interface also includes a DC offset correction loop of the input data receiver path. The level shifting circuit operates by sensing the incoming common mode voltage of a differential data signal with a resistor divider and sampling the difference between the measured input common mode voltage and desired input differential voltages generated by a differential DAC in the DC offset correction loop on two small capacitors. The small capacitors are switched across larger in-signal-path capacitors cyclically, so that over time a charge will build up to give the desired level shift to shift the common mode voltage of the incoming signal to the level tolerable by low voltage high speed transistors in the receiving integrated circuit.

摘要翻译： 例如，可操作以用于集成电路之间的高速差分数据传输的串行接口使用开关电容器技术提供输入数据信号的电平移位，该开关电容器技术以最小的衰减和最小的带宽减小来平移共模电压。 串行接口还包括输入数据接收器路径的DC偏移校正循环。 电平移位电路通过用电阻分压器感测差分数据信号的输入共模电压来进行工作，并对两路中的DC偏移校正回路中由差分DAC产生的所需输入差分电压之间的差进行采样 小电容器。 小电容器周期性地切换到较大的信号通路电容器上，因此随着时间的推移，电荷将建立起来以产生期望的电平移位，以将输入信号的共模电压转换为由低电压高速晶体管容许的电平 在接收集成电路中。

公开(公告)号：US07675447B1

公开(公告)日：2010-03-09

申请号：US12154611

申请日：2008-05-24

申请人： David S. Coulson

发明人： David S. Coulson

IPC分类号： H03M3/00

CPC分类号： H03M3/494

摘要： A microcontroller has a compact 8-bit processor and a differential input sigma-delta ADC (SDADC). In a low-cost pyroelectric sensor motion detector application, a sensor output signal is supplied onto a second differential input of the SDADC. A first programmable internal reference voltage source supplies VREF1 via an internal signal path onto a first differential input of the SDADC. A second programmable internal reference voltage source supplies VREF2 onto a reference voltage input of the SDADC. VREF1 sets the center of the SDADC input sample window, thereby avoiding the need to provide an external AC blocking capacitor. VREF2 sets the size of the window. Proper window sizing and sample averaging and the high-resolution SDADC obviate the need for input signal amplification. Throughput requirements on the 8-bit processor are reduced by providing a hardware averager and associated DMA controller, thereby making the overall solution a low-cost, noise-insensitive, solution.

摘要翻译： 微控制器具有紧凑的8位处理器和差分输入Σ-ΔADC（SDADC）。 在低成本的热电传感器运动检测器应用中，传感器输出信号被提供到SDADC的第二差分输入端。 第一个可编程内部参考电压源通过内部信号路径将VREF1提供给SDADC的第一个差分输入。 第二个可编程内部参考电压源将VREF2提供给SDADC的参考电压输入。 VREF1设置SDADC输入采样窗口的中心，从而避免需要提供外部交流隔离电容。 VREF2设置窗口的大小。 适当的窗口大小和采样平均以及高分辨率SDADC可以避免输入信号放大的需要。 通过提供硬件平均器和相关的DMA控制器来减少对8位处理器的吞吐量要求，从而使整体解决方案成为低成本，噪声不敏感的解决方案。

公开(公告)号：US07212587B2

公开(公告)日：2007-05-01

申请号：US10343540

申请日：2001-07-16

申请人： Nadim Khlat ,  Francois Dorel

发明人： Nadim Khlat ,  Francois Dorel

IPC分类号： H04L25/06

CPC分类号： H04L25/063 ,  H03F1/304 ,  H03F2200/375 ,  H03M3/428 ,  H03M3/456 ,  H03M3/494

摘要： Apparatus for reducing DC offset in a signal path of a conversion system comprising a front end circuit for providing an input signal having an a DC offset; an amplifier system coupled to the front end circuit to receive and amplify the input signal; a multi-bit sigma delta modulator for receiving the input signal from the amplifier system and providing a first bit quantizer; a DC adapt circuit coupled to the sigma delta modulator for receiving the first bit quantizer from the sigma delta modulator and for providing an operation to reduce DC offset; a digital to analog converter (DAC) coupled to the digital DC adapt circuit to provide an analog signal representative of the DC offset correction to the input of the amplifier system, wherein the digital DC adapt circuit and the DAC form a feedback path originating at the first bit of the multi bit sigma delta modulator to the input of the amplifier system.

摘要翻译： 用于减小转换系统的信号路径中的DC偏移的装置，包括用于提供具有DC偏移的输入信号的前端电路; 耦合到前端电路以接收和放大输入信号的放大器系统; 多位Σ-Δ调制器，用于从放大器系统接收输入信号并提供第一位量化器; 耦合到所述Σ-Δ调制器的DC适配电路，用于从所述Σ-Δ调制器接收所述第一位量化器并提供减少DC偏移的操作; 耦合到所述数字DC适配器电路的数模转换器（DAC），以向所述放大器系统的输入提供表示所述DC偏移校正的模拟信号，其中所述数字DC适配电路和所述DAC形成源自所述放大器系统的反馈路径 多位Σ-Δ调制器的第一位到放大器系统的输入端。

公开(公告)号：US06891430B1

公开(公告)日：2005-05-10

申请号：US09695706

申请日：2000-10-25

申请人： Axel Thomsen ,  Edwin De Angel ,  Sherry Wu ,  Lei Wang ,  Aryesh Amar

发明人： Axel Thomsen ,  Edwin De Angel ,  Sherry Wu ,  Lei Wang ,  Aryesh Amar

IPC分类号： H03M3/00 ,  G06G7/12

CPC分类号： H03M3/494 ,  H03M3/43 ,  H03M3/448 ,  H03M3/452

摘要： A signal processing integrated circuit has having a chopper stabilized, multistage, feedforward amplifier and a delta sigma analog to digital converter. Filtering of the output of the output from the analog to digital converter comprises a sinc5 filter and a sinc3 filter. The sinc3 filter may be bypassed. A rough buffer permits quick charging of a sample and hold capacitor during part of the charge cycle and slower but more accurate charging during the remainder of the charge cycle.

摘要翻译： 信号处理集成电路具有斩波稳定的多级前馈放大器和ΔΣ模数转换器。 从模数转换器输出的输出的滤波包括​​一个Sinc＆lt; 5＆gt;滤波器和一个sinc＆lt; 3＆gt; 3滤波器。 可以绕过sinc <3> 3滤波器。 一个粗略的缓冲器允许在充电周期的一部分期间快速充电一个采样和保持电容器，并且在充电周期的剩余时间内可以进行更慢但更精确的充电。

公开(公告)号：US20040071238A1

公开(公告)日：2004-04-15

申请号：US10343540

申请日：2003-05-12

发明人： Nadim Khlat ,  Francois Dorel

IPC分类号： H04L001/00 ,  H03D001/04

CPC分类号： H04L25/063 ,  H03F1/304 ,  H03F2200/375 ,  H03M3/428 ,  H03M3/456 ,  H03M3/494

摘要： Apparatus for reducing DC offset in a signal path of a conversion system comprising a front end circuit for providing an input signal having an a DC offset; an amplifier system coupled to the front end circuit to receive and amplify the input signal; a multi-bit sigma delta modulator for receiving the input signal from the amplifier system and providing a first bit quantizer; a DC adapt circuit coupled to the sigma delta modulator for receiving the first bit quantizer from the sigma delta modulator and for providing an operation to reduce DC offset; a digital to analog converter (DAC) coupled to the digital DC adapt circuit to provide an analog signal representative of the DC offset correction to the input of the amplifier system, wherein the digital DC adapt circuit and the DAC form a feedback path originating at the first bit of the multi bit sigma delta modulator to the input of the amplifier system.

摘要翻译： 用于减小转换系统的信号路径中的DC偏移的装置，包括用于提供具有DC偏移的输入信号的前端电路; 耦合到前端电路以接收和放大输入信号的放大器系统; 多位Σ-Δ调制器，用于从放大器系统接收输入信号并提供第一位量化器; 耦合到所述Σ-Δ调制器的DC适配电路，用于从所述Σ-Δ调制器接收所述第一位量化器并提供减少DC偏移的操作; 耦合到所述数字DC适配器电路的数模转换器（DAC），以向所述放大器系统的输入提供表示所述DC偏移校正的模拟信号，其中所述数字DC适配电路和所述DAC形成源自所述放大器系统的反馈路径 多位Σ-Δ调制器的第一位到放大器系统的输入端。