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21 条记录 (耗时 0.031 秒)

    Techniques for signal measurement using a conditionally stable amplifier
    1.
    发明授权
    Techniques for signal measurement using a conditionally stable amplifier 有权
    使用条件稳定放大器进行信号测量的技术

    公开(公告)号：US06891430B1

    公开(公告)日：2005-05-10

    申请号：US09695706

    申请日：2000-10-25

    申请人： Axel Thomsen ,  Edwin De Angel ,  Sherry Wu ,  Lei Wang ,  Aryesh Amar

    发明人： Axel Thomsen ,  Edwin De Angel ,  Sherry Wu ,  Lei Wang ,  Aryesh Amar

    IPC分类号： H03M3/00 ,  G06G7/12

    CPC分类号： H03M3/494 ,  H03M3/43 ,  H03M3/448 ,  H03M3/452

    摘要： A signal processing integrated circuit has having a chopper stabilized, multistage, feedforward amplifier and a delta sigma analog to digital converter. Filtering of the output of the output from the analog to digital converter comprises a sinc5 filter and a sinc3 filter. The sinc3 filter may be bypassed. A rough buffer permits quick charging of a sample and hold capacitor during part of the charge cycle and slower but more accurate charging during the remainder of the charge cycle.

    摘要翻译： 信号处理集成电路具有斩波稳定的多级前馈放大器和ΔΣ模数转换器。 从模数转换器输出的输出的滤波包括​​一个Sinc＆lt; 5＆gt;滤波器和一个sinc＆lt; 3＆gt; 3滤波器。 可以绕过sinc <3> 3滤波器。 一个粗略的缓冲器允许在充电周期的一部分期间快速充电一个采样和保持电容器，并且在充电周期的剩余时间内可以进行更慢但更精确的充电。

    Integrated circuit with a mode control selecting settled and unsettled output from a filter
    3.
    发明授权
    Integrated circuit with a mode control selecting settled and unsettled output from a filter 有权
    具有模式控制的集成电路，从滤波器选择稳定和未稳定的输出

    公开(公告)号：US06857002B1

    公开(公告)日：2005-02-15

    申请号：US09695704

    申请日：2000-10-25

    申请人： Axel Thomsen ,  Jerome E. Johnston ,  Edwin De Angel ,  Aryesh Amar

    发明人： Axel Thomsen ,  Jerome E. Johnston ,  Edwin De Angel ,  Aryesh Amar

    IPC分类号： G06F13/00 ,  G06F17/10 ,  H03H17/02 ,  H03M3/02

    CPC分类号： H03H17/0294 ,  H03M3/392 ,  H03M3/462

    摘要： In a signal processing integrated circuit having an analog to digital converter and a digital filter having a plurality of taps separated in time, when starting a conversion after a reset or a change of input channel, the filter will have an incomplete set of input data as the delayed inputs to an output calculation are all zero from the reset operation. After reset, during the time that data are filling up the filter pipeline, the calculation of an output value will give a result that holds information about the input, but does not present the data with the same scaling and frequency content as the fully settled filter. The integrated circuit selectively provides two modes, on that provides only fully settled data from the filter or and another that provides all data from the filter, including unsettled data. Knowledge about the filter coefficients can be utilized by a user or user process to extract information about the input from the unsettled data.

    摘要翻译： 在具有模拟数字转换器的信号处理集成电路和具有时间分离的多个抽头的数字滤波器的情况下，当在复位或输入通道改变之后开始转换时，滤波器将具有不完整的输入数据集 输出计算的延迟输入从复位操作全部为零。 在复位之后，在数据填满过滤器管线的时间期间，输出值的计算将给出保存有关输入信息的结果，但不显示具有与完全设置的过滤器相同的缩放和频率内容的数据 。 集成电路有选择地提供两种模式，其中仅提供来自滤波器的完全确定的数据，或者提供来自滤波器的所有数据的另一种模式，包括不稳定的数据。 关于滤波器系数的知识可以由用户或用户进程利用来从未解决的数据中提取关于输入的信息。

    Sinc filter with selective decimation ratios
    6.
    发明授权
    Sinc filter with selective decimation ratios 有权
    具有选择性抽取比例的Sinc滤波器

    公开(公告)号：US06317765B1

    公开(公告)日：2001-11-13

    申请号：US09153862

    申请日：1998-09-16

    申请人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    发明人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    IPC分类号： G06F1717

    CPC分类号： H03H17/0282 ,  H03H17/0226 ,  H03H17/0664

    摘要： A decimation filter implements selective decimation ratios by arranging a plurality of sinc filters in different pipeline arrangements to produce the desired ratio. Power savings area achieved by implementing the sinc filters as FIR sinc filters and by implementing multiplications using look up tables. One approach uses a fixed first stage filter and one or more second stage sinc filters selected from the group comprising two 4th order, 5 tap sinc filters, a 4th order, 9 tap sinc filter; a 5th order, 6 tap sinc filter and a 6th order 7 tap sinc filter. The sinc filter is particularly useful applications in the field of data acquisition and particularly in the area of seismic sensing.

    摘要翻译： 抽取滤波器通过在不同的流水线布置中布置多个正弦滤波器来实现选择性抽取比，以产生期望的比率。 通过将sinc滤波器实现为FIR sinc滤波器并通过使用查找表来实现乘法而实现的省电区域。 一种方法使用固定的第一级滤波器和一个或多个第二级sinc滤波器，其选自包括两个4阶，5抽头sinc滤波器，第4级，9抽头sinc滤波器的组; 5号，6抽头sinc过滤器和6阶7抽头sinc过滤器。 sinc滤波器在数据采集领域尤其是在地震检测领域尤其有用。

    Correct carry bit generation
    7.
    发明授权
    Correct carry bit generation 失效
    正确的进位位产生

    公开(公告)号：US06243733B1

    公开(公告)日：2001-06-05

    申请号：US09153868

    申请日：1998-09-16

    申请人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    发明人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    IPC分类号： G06F738

    CPC分类号： G06F7/5443 ,  G06F7/49947

    摘要： A multiply add carry (MAC) circuit correctly determines the value of a carry bit when an operation X*Y+Z is undertaken, where X, Y and Z are real numbers and where an accumulator and rounding are utilized. The circuit (1) determines if the product X*Y is negative, (2) determines if the value in the accumulator is negative, (3) determines if a round bit propagates all the way to the most significant bit (MSB) position, (4) determines if the result X*Y+Accumulator+round is negative; and (5) determines a correct carry bit based on the other determinations.

    摘要翻译： 当进行X * Y + Z操作时，乘法加法（MAC）电路正确地确定进位位的值，其中X，Y和Z是实数，并且使用累加器和舍入。 电路（1）确定乘积X * Y是否为负，（2）确定累加器中的值是否为负，（3）确定一个圆比特是否一直传播到最高有效位（MSB）位置， （4）确定结果X * Y +累加器+圆是否为负; 和（5）基于其他确定来确定正确的进位位。

    Network synchronization
    8.
    发明授权
    Network synchronization 有权
    网络同步

    公开(公告)号：US07218612B2

    公开(公告)日：2007-05-15

    申请号：US10457113

    申请日：2003-06-09

    申请人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    发明人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    IPC分类号： H04L12/26 ,  G01V1/00

    CPC分类号： H04J3/0682 ,  G01V1/22

    摘要： A network arrangement uses a poll select control protocol and a loop back arrangement at each node for equalizing transmission delay from each node to a central station. Delays at each node can be adjusted to start timing in response to a broadcast signal indicating an amount of delay to be applied from the start of a synchronization interval to the beginning of transmission of data collected at the nodes. The arrangement is particularly useful in the field of data acquisition and particularly in the area of seismic sensing.

    摘要翻译： 网络布置在每个节点处使用轮询选择控制协议和循环布置来均衡从每个节点到中心站的传输延迟。 可以调整每个节点的延迟以响应于指示从同步间隔开始到在节点处收集的数据的传输的开始而应用的延迟量的广播信号。 该方案在数据采集领域尤其在地震检测领域特别有用。

    Power on reset techniques for an integrated circuit chip
    9.
    发明授权
    Power on reset techniques for an integrated circuit chip 有权
    集成电路芯片的上电复位技术

    公开(公告)号：US06980037B1

    公开(公告)日：2005-12-27

    申请号：US09153864

    申请日：1998-09-16

    申请人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    发明人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    IPC分类号： H03L3/00 ,  H03L7/00 ,  H03L7/06

    CPC分类号： H03L7/06 ,  H03L3/00

    摘要： A power on reset circuit, preferably for an integrated circuit, detects application of voltage, starts a phase locked loop one application of voltage is detected but inhibits all clock used for digital logic operations until voltage stability is achieved. If a switched converter is used, the duty cycle of the switched converter is held at unity for a period of time before it is set to that needed to achieve the desired chip operating voltage. Clocks controlling other circuits can be released in stages after the duty cycle of the switched converter is set to its operating voltage level.

    摘要翻译： 上电复位电路，优选用于集成电路，检测电压的施加，启动锁相环，检测到电压的一个应用，但是抑制用于数字逻辑运算的所有时钟，直到达到电压稳定。 如果使用开关转换器，则在将其设置为实现期望的芯片工作电压所需的时间之前，将开关转换器的占空比保持在一定的时间。 在切换转换器的占空比被设置为其工作电压电平之后，可以分阶段释放控制其它电路的时钟。

    Noise management using a switched converter
    10.
    发明授权
    Noise management using a switched converter 有权
    使用开关转换器进行噪声管理

    公开(公告)号：US06281718B1

    公开(公告)日：2001-08-28

    申请号：US09154241

    申请日：1998-09-16

    申请人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    发明人： Joel Page ,  Edwin De Angel ,  Wai Laing Lee ,  Lei Wang ,  Hong Helena Zheng ,  Chung-Kai Chow

    IPC分类号： H03B2100

    CPC分类号： H02M3/1588 ,  Y02B70/1466

    摘要： A switched converter uses two series connected complementary CMOS devices and has a square wave source for activating one CMOS device while deactivating the other; and a break before make circuit connected between the square wave source and said complementary CMOS devices to ensure that one device is substantially completely off before the other device turns on. The switched converter is programmable as to frequency, phase and duty cycle.

    摘要翻译： 开关转换器使用两个串联的互补CMOS器件，并具有用于激活一个CMOS器件的方波源，同时使另一个CMOS器件失效; 以及在使电路连接在方波源和所述互补CMOS器件之间的断路，以确保在另一器件接通之前一个器件基本上完全截止。 开关转换器可编程为频率，相位和占空比。