利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

120 条记录 (耗时 0.018 秒)

    Custom metametadata with packagable records
    61.
    发明授权
    Custom metametadata with packagable records 有权

    公开(公告)号：US10146510B2

    公开(公告)日：2018-12-04

    申请号：US13933776

    申请日：2013-07-02

    申请人： salesforce.com, inc.

    发明人： Avrom Roy-Faderman

    IPC分类号： G06F9/44 ,  G06F8/00 ,  G06F9/54

    摘要： Techniques for providing custom metadata in a multi-tenant database environment in which hardware and software of the multi-tenant database system is shared by one or more organizations, each having one or more corresponding users. Each of the organizations has associated organization data and organization metadata. Activating procedural code is triggered in response to a trigger event determined by a platform interface. The procedural code is to query the organization metadata provided by the associated organization through a metadata interface provided by a platform developer. The platform interface is provided by the platform developer and the procedural code utilizes compile time dependencies to generate custom metametadata to be maintained by the platform developer and to be provided to the organizational metadata, which is to be maintained by the corresponding organization. The organization data owned by the organization is written to with the procedural code in response to results of the query.

    Computerized method and end-to-end “pilot as a service” system for controlling start-up/enterprise interactions
    62.
    发明授权
    Computerized method and end-to-end “pilot as a service” system for controlling start-up/enterprise interactions 有权

    公开(公告)号：US10140206B2

    公开(公告)日：2018-11-27

    申请号：US15347191

    申请日：2016-11-09

    申请人： PROOV SYSTEMS LTD.

    发明人： Alexey Sapozhnikov ,  Toby Olshanetsky

    IPC分类号： G06F11/36 ,  G06F8/00 ,  G06F8/60 ,  G06F11/34 ,  G06F17/30

    摘要： An end-to-end “pilot as service” system for software pilot testing, comprising a server including at least one processor and operative for generating a set of software testing environment/s simultaneously serving plural clients from among a first plurality of enterprise clients, the environment being operative for concurrently running plural proof-of-concept tests for respective plural software products each being tested (“pilots”), on behalf of an individual start-up client from among a second plurality of start-up clients, by an individual one of the population of enterprise clients; a registration functionality, on the processor, operative for pre-registering at least one of: enterprise clients from among the first plurality of enterprise clients, and start-up clients from among the second plurality of start-up clients; and a dashboard functionality, on the processor, operative for presenting at least one result of at least one proof-of-concept test to each client which has pre-registered using said registration functionality.

    Memory having increased data-transfer speed and related systems and methods
    66.
    发明授权
    Memory having increased data-transfer speed and related systems and methods 失效
    内存具有增加的数据传输速度和相关的系统和方法

    公开(公告)号：US07290117B2

    公开(公告)日：2007-10-30

    申请号：US10032109

    申请日：2001-12-20

    申请人： Erik E. Erlandson ,  David A. Tremblay, Jr.

    发明人： Erik E. Erlandson ,  David A. Tremblay, Jr.

    IPC分类号： G06F12/00 ,  G06F8/00

    CPC分类号： G11C7/1021 ,  G11C2207/2281 ,  G11C2207/229

    摘要： A memory includes an address bus, address counter, address decoder, comparator, and control circuit. During a data read or write cycle, the address bus receives an external address, the address counter generates an internal address, which the address decoder decodes, and the comparator compares the external address to a value. Based on the relationship between the external address and the value, the comparator enables or disables the data transfer. For example, such a memory can terminate a page-mode read/write cycle by determining when the current external column address is no longer equal to the current internal column address. This allows the system to terminate the cycle after a predetermined number of data transfers by setting the external column address to a value that does not equal the internal column address. Or, the comparator can compare the external or internal address to a predetermined end address, and the memory can terminate the cycle when the external or internal address equals the end address.

    摘要翻译： 存储器包括地址总线，地址计数器，地址解码器，比较器和控制电路。 在数据读或写周期期间，地址总线接收外部地址，地址计数器产生一个内部地址，地址解码器解码，比较器将外部地址与一个值进行比较。 基于外部地址和值之间的关系，比较器启用或禁用数据传输。 例如，这样的存储器可以通过确定当前外部列地址何时不再等于当前内部列地址来终止页模式读/写周期。 这允许系统通过将外部列地址设置为不等于内部列地址的值来在预定数量的数据传输之后终止循环。 或者，比较器可以将外部或内部地址与预定的结束地址进行比较，并且当外部或内部地址等于结束地址时，存储器可以终止循环。