公开(公告)号：US5331670A

公开(公告)日：1994-07-19

申请号：US830036

申请日：1992-01-31

Applicant: Massimo Sorbara ,  Jean-Jacques Werner

Inventor： Massimo Sorbara ,  Jean-Jacques Werner

IPC: H04L7/06 ,  H04J3/07 ,  H04L7/08 ,  H04L27/34 ,  H04L27/38 ,  H04L7/04

CPC classification number: H04L27/3477 ,  H04J3/07

Abstract: A synchronization scheme for a digital communications system wherein customer data is connected to a synchronous communications network utilizes auxiliary symbols to provide frame synchronization. Each such auxiliary symbol lies outside of a conventional symbol constellation and is only used to represent framing information. Variations of the customer data rate relative to an expected rate are compensated for by the use of stuff and delete bits in each frame. These bits can be either customer data bits or ancillary bits depending on the direction of this variation. Advantageously, the auxiliary symbols also provide a determination of whether the stuff and delete bits in any frame are customer data or ancillary bits.

Abstract translation: 其中客户数据连接到同步通信网络的数字通信系统的同步方案利用辅助符号来提供帧同步。 每个这样的辅助符号位于常规符号星座之外，并且仅用于表示成帧信息。 通过使用每个帧中的填充和删除位来补偿客户数据速率相对于期望速率的变化。 根据该变化的方向，这些位可以是客户数据位或辅助位。 有利地，辅助符号还提供确定任何帧中的填充和删除位是客户数据还是辅助位。

公开(公告)号：US5313502A

公开(公告)日：1994-05-17

申请号：US697778

申请日：1991-05-09

Applicant: Rainer Nawrocki ,  Siegfried Brunle ,  Wolfgang Ehrlich

Inventor： Rainer Nawrocki ,  Siegfried Brunle ,  Wolfgang Ehrlich

IPC: H04J3/07 ,  H04L25/36

CPC classification number: H04J3/076

Abstract: A circuit arrangement for imaging a useful digital signal from a frame of a first digital signal having a first bit rate into a frame of a second digital signal having a second bit rate, where the useful digital signal had been written into a first elastic memory and then read out of the first elastic memory in the frame of the first digital signal using a pulse stuffing technique, and with the frame of the first digital signal containing data representing the average fill level of the first elastic memory. The arrangement includes a second elastic memory, a frame detector for detecting the frame of the first signal and controlling activation of write-in of the useful digital signal from the frame of the first digital signal to the second elastic memory, and a frame generator which generates the frame of the second digital signal and controls activation of stuffing and of read-out of the useful digital signal from the second elastic memory into the frame of the second digital signal. An integrator determines the average fill level of the second elastic memory and a subtracter determines the difference between the average fill levels of the first and second elastic memories. This digital difference is fed to a digital control circuit, which includes a digital filter and a pulse density modulator that makes a stuffing decision as a function of the output of the digital filter. Each stuffing decision is input to the frame generator.

Abstract translation: 一种电路装置，用于将有用的数字信号从具有第一比特率的第一数字信号的帧成像到具有第二比特率的第二数字信号的帧中，其中有用数字信号已被写入第一弹性存储器， 然后使用脉冲填充技术读出第一数字信号的帧中的第一弹性存储器，并且第一数字信号的帧包含表示第一弹性存储器的平均填充水平的数据。 该装置包括第二弹性存储器，用于检测第一信号的帧并控制有用数字信号从第一数字信号的帧到第二弹性存储器的写入的激活的帧检测器，以及帧生成器 产生第二数字信号的帧，并且控制从第二弹性存储器到第二数字信号的帧的填充和读出有用数字信号的激活。 积分器确定第二弹性存储器的平均填充水平，减法器确定第一和第二弹性存储器的平均填充水平之间的差。 该数字差异被馈送到数字控制电路，数字控制电路包括数字滤波器和脉冲密度调制器，其作为数字滤波器的输出的函数进行填充决定。 每个填充决定都输入到帧生成器。

公开(公告)号：US5305322A

公开(公告)日：1994-04-19

申请号：US3832

申请日：1993-01-08

Applicant: Eiichi Kabaya ,  Kenichi Kurokawa

Inventor： Eiichi Kabaya ,  Kenichi Kurokawa

IPC: H04J3/07 ,  H04J3/06 ,  H04Q11/04 ,  H04Q11/08

CPC classification number: H04J3/0623 ,  H04Q11/08 ,  H04J2203/0089

Abstract: In a stuff-synchronized time division multiplex (TDM) transmission system, an incoming TDM signal is delayed so that a plurality of TDM frame sequences are successively delayed by one time slot and appear at the inputs of a data selector. A control circuit is provided for deriving a channel-by-channel selection signal from stuff specification bits contained in the incoming TDM signal. The data selector is responsive to the selection signal to select a channel in one of the TDM frame sequences and delivers the selected channel as a TDM output signal to a time division switch, or cross-connect in which it is decomposed into channels for switching to a desired route.

Abstract translation: 在填充同步时分复用（TDM）传输系统中，进入的TDM信号被延迟，使得多个TDM帧序列被连续延迟一个时隙并出现在数据选择器的输入端。 提供控制电路，用于从包含在输入TDM信号中的填充规格位导出逐通道选择信号。 数据选择器响应选择信号选择TDM帧序列中的一个信道，并将选择的信道作为TDM输出信号传送到时分交换机，或者交叉连接，其中它被分解为用于切换到 所需的路线。

公开(公告)号：US5297180A

公开(公告)日：1994-03-22

申请号：US805465

申请日：1991-12-10

Applicant: Daniel C. Upp ,  Dan H. Wolaver

Inventor： Daniel C. Upp ,  Dan H. Wolaver

IPC: G06F5/06 ,  H04J3/00 ,  H04J3/07 ,  H04J3/16 ,  H04L7/02 ,  H04L7/00

CPC classification number: G06F5/06 ,  H04J3/076 ,  H04J3/1611 ,  G06F2205/061 ,  G06F2205/123

Abstract: A digital clock dejitter circuit has a RAM for receiving an incoming gapped signal, a digital, fractional RAM fullness gauge for tracking the average input and output rates to and from the RAM and for generating therefrom a control indication, and a controllable digital frequency generator for receiving a fast clock signal and the control indication, and for providing therefrom a substantially jitter-free clock signal at the same nominal rate as the incoming gapped signal. The RAM fullness gauge has write and read counters which track the movement of data into and out of the RAM, and a subtractor for taking the difference of the counters to obtain the integer value of the RAM depth. The controllable digital frequency generator has an adder, a register, and a fast clock counter (FCC) which provides the fullness gauge with a fractional digital indication of the RAM depth. The adder has a carry output fed to the FCC to control whether the FCC divides by x or x+1, and a remainder output fed to the register and then fed back as an input to the adder. The adder also receives the control indication from the fullness gauge as an input. FCC inputs include the fast clock, and the carry output of the adder. The FCC outputs are a read signal for causing a byte to be read from the RAM at the end of a count cycle, and the fast clock count used for fractional fullness.

Abstract translation: 数字时钟去抖电路具有用于接收输入间隙信号的RAM，用于跟踪来自RAM和从其产生控制指示的平均输入和输出速率的数字分数RAM饱和度计，以及可控数字频率发生器， 接收快速时钟信号和控制指示，并且向其提供与入射间隙信号相同的额定速率下的基本上无抖动的时钟信号。 RAM充满度计具有写入和读取计数器，其跟踪数据进出RAM的移动，以及减法器，用于获取计数器的差异以获得RAM深度的整数值。 可控数字频率发生器具有加法器，寄存器和快速时钟计数器（FCC），其向饱和度计提供RAM深度的分数字数字指示。 加法器具有馈送到FCC的进位输出，用于控制FCC是否将x除x或x + 1，剩余输出馈送到寄存器，然后作为输入反馈给加法器。 加法器还从饱和度计作为输入接收控制指示。 FCC输入包括快速时钟和加法器的进位输出。 FCC输出是一个读取信号，用于在计数周期结束时从RAM读取一个字节，并且快速时钟计数用于分数饱和。

公开(公告)号：US5289507A

公开(公告)日：1994-02-22

申请号：US857928

申请日：1992-05-13

Applicant: Daniel C. Upp

Inventor： Daniel C. Upp

IPC: G06F5/06 ,  H04J3/00 ,  H04J3/07 ,  H04J3/16 ,  H04L7/02 ,  H04L7/00 ,  H04J3/06

CPC classification number: H04J3/1611 ,  G06F5/06 ,  H04J3/076 ,  G06F2205/061 ,  G06F2205/123

Abstract: Clock dejitter circuits are provided and comprise control circuits for generating a plurality of pulses over a clock cycle, and clock circuits for tracking the speeds of jittered incoming data signal and based on those speeds, and utilizing the plurality of pulses generating substantially unjittered data signals at the nominal rates of the jittered incoming signals. A control circuit broadly includes a divide by value x-divide by value x+1 circuit which receives a fast input clock signal, a modulus y counter, and a count decode for providing z control pulses over the count of y, and a logic gate for taking the outputs from the count decode and controlling the divide block to guarantee hat the divide block divides the fast input clock signal by value x q times for every r times the divide block divides the fast input clock signal by value x+1; wherein q plus r equals y, and z equals either q+1 or r+1.

Abstract translation: 提供时钟分离电路并且包括用于在时钟周期上产生多个脉冲的控制电路，以及用于跟踪抖动的输入数据信号的速度并基于那些速度的时钟电路，以及利用产生基本上未抖动的数据信号的多个脉冲 惊人的进入信号的标称速率。 控制电路广泛地包括接收快速输入时钟信号的值x + 1电路除数x分频，模y计数器和用于在y的计数上提供z控制脉冲的计数解码，以及逻辑门 为了从计数解码和控制分割块获取输出，以确保除法器块将快速输入时钟信号除以每x r次的xq倍，除法将快速输入时钟信号除以值x + 1; 其中q加r等于y，z等于q + 1或r + 1。

公开(公告)号：US5280502A

公开(公告)日：1994-01-18

申请号：US782710

申请日：1991-10-25

Applicant: Michael Niegel ,  Ralph Urbansky ,  Miguel Robledo

Inventor： Michael Niegel ,  Ralph Urbansky ,  Miguel Robledo

IPC: H04J3/07 ,  H04L7/00

CPC classification number: H04J3/076

Abstract: The described circuit arrangement for removing stuff bits from a frame-structured signal which is available in n parallel bits, comprises a memory circuit (2) which is supplied with the parallel bits (1b). The memory circuit (2) is followed by a controllable selection circuit (3) having n outputs (3a). A control circuit (9) produces control signals (9b, 9c), which determine which bits stored in the memory circuit are transported to the n outputs (3a) of the selection circuit (3). The memory circuit (2) comprises only n delay elements by which each of the n parallel bits (1b) is delayed for the duration of one bit. So as to provide that n delay elements will be sufficient, the control circuit (9) is to block at predetermined time intervals the acceptance of new bits in one or a plurality of delay elements.

Abstract translation: 所描述的用于从每个情况下以n个并行比特发生的帧结构信号中去除填充比特的电路包含存储电路（2），并行比特（1b）被提供给该存储器电路。 具有n个输出（3a）的可控选择电路（3）连接到存储电路（2）的下游。 控制电路（9）产生控制信号（9a，9b，9c），用于确定存储在存储器电路中的哪一个位被转发到选择电路（3）的n个输出端（3a）。 存储器电路（2）仅由n个延迟分量组成，其中n个并行比特（1b）中的每一个延迟一位的持续时间。 为了确保n个延迟分量足够，控制电路（9）必须防止一个或多个延迟分量在预定时间内接受新的比特。

公开(公告)号：US5260940A

公开(公告)日：1993-11-09

申请号：US628793

申请日：1990-12-17

Applicant: Ralph Urbansky

Inventor： Ralph Urbansky

IPC: G06F5/12 ,  G06F5/10 ,  H04J3/00 ,  H04J3/07 ,  H04L7/00

CPC classification number: G06F5/10 ,  H04J3/076 ,  G06F2205/061

Abstract: A circuit arrangement for adapting the bit rates of two signals to each other and which comprises an elastic store (6). The useful data of a first frame-structured signal are written into this store (6) by means of a write address counter (7) and read out again by means of a read address counter (8). A phase comparator (16) is used for comparing the counts of these counters (7,8). In order to largely avoid jitter in the signal that has been read, a balancing counter (14) is provided which, on average, is stopped as often as the write address counter (7) is, but runs more smoothly than the write address counter. The means for controlling the operation of the balancing counter (14) comprise comparator circuits (12E, 12F, 12G) by means of which the operation of the frame counter (12) is monitored, an up/down counter (19) as well as various gates (11, 13, 17, 18). The phase comparator (16) compares the count of the balancing counter (14 ) to the count of the read address counter (8) and the output signal of the phase comparator (16) is used for producing the clock for the read address counter (8).

Abstract translation: 一种用于将两个信号的比特率彼此适配并且包括弹性存储器（6）的电路装置。 通过写地址计数器（7）将第一帧结构信号的有用数据写入该存储器（6），并通过读地址计数器（8）再次读出。 相位比较器（16）用于比较这些计数器（7,8）的计数。 为了大大地避免已经读取的信号中的抖动，提供平衡计数器（14），平衡计数器（14）平均被停止，如同写入地址计数器（7）那样频繁地运行，但比写入地址计数器运行更平稳 。 用于控制平衡计数器（14）的操作的装置包括比较器电路（12E，12F，12G），通过该比较器电路监视帧计数器（12）的操作，上/下计数器（19）以及 各种门（11,13,17,18）。 相位比较器（16）将平衡计数器（14）的计数与读地址计数器（8）的计数进行比较，并且相位比较器（16）的输出信号用于产生读地址计数器的时钟 8）。

公开(公告)号：US5245636A

公开(公告)日：1993-09-14

申请号：US776437

申请日：1991-10-17

Applicant: Hikmet Sari ,  Georges M. Karam

Inventor： Hikmet Sari ,  Georges M. Karam

IPC: H04J3/07

CPC classification number: H04J3/076

Abstract: A device for reducing the jitter caused by pointer adjustments in a digital telecommunication network comprising of a circuit inserting in the vicinity of each phase step caused by a pointer adjustment, a plurality of smoothing phase steps in accordance with a deterministic smoothing pattern in order to eliminate, after having passed through a conventional desynchronizer, the quantifying effects of the phase steps. Provision also is made, for the case in which each phase step caused by a pointer adjustment comprises a plurality of bits, in that a control circuit is present to resolve the step into a plurality of elementary steps and to control the insertion of these steps in a manner matched to the rate of occurrence of pointer adjustments. In particular, the device applies to networks based on Synchronous Digital Hierarchy.

Abstract translation: 一种用于减少由数字电信网络中的指针调整引起的抖动的装置，包括由指针调整引起的每个相位步骤附近插入的电路，根据确定性平滑模式的多个平滑相位步骤，以消除 在通过常规的去同步器之后，相位步骤的量化效果。 对于由指针调整引起的每个相位步骤包括多个位的情况也是如此，其中存在控制电路以将步骤解析为多个基本步骤并且控制这些步骤的插入 与指针调整的发生率相匹配的方式。 具体来说，该设备适用于基于同步数字体系的网络。

公开(公告)号：US5052031A

公开(公告)日：1991-09-24

申请号：US567490

申请日：1990-08-14

Applicant: Nicholas J. Molloy

Inventor： Nicholas J. Molloy

IPC: H03L7/06 ,  H03L7/099 ,  H03L7/197 ,  H04J3/07

CPC classification number: H03L7/197 ,  H03L7/0992 ,  H04J3/076

Abstract: A digital phase locked loop is employed to realize an output clock signal from a reference signal having a frequency which is not an integer multiple of the output clock signal frequency. This is realized by employing a programmable divider for dividing the reference signal which is dynamically controlled by a controllably variable base divisor. The base divisor control is responsive to the reference signal and to a phase error signal. The base divisor is generated to obtain a desired fractional division of the reference signal frequency and in a manner to minimize the amplitude of any resulting "high" frequency jitter in the output clock signal from the loop.

公开(公告)号：US5052025A

公开(公告)日：1991-09-24

申请号：US572740

申请日：1990-08-24

Applicant: Donald G. Duff ,  Donald A. Lane ,  Ricardo Mediavilla

Inventor： Donald G. Duff ,  Donald A. Lane ,  Ricardo Mediavilla

IPC: H04L7/00 ,  H04J3/00 ,  H04J3/06 ,  H04J3/07 ,  H04L5/24

CPC classification number: H04J3/076 ,  H04L5/24 ,  Y10S370/907

Abstract: Improved jitter performance is realized in a desynchronizer for obtaining an asynchronous digital signal, e.g., a DS3 signal, from a received synchronous digital signal, e.g., a SONET STS-1 signal. The improved jitter performance results from the use of a unique adaptive bit leaking arrangement in conjunction with a digital phase locked loop and synchronizing elastic store. An estimate of a bit leaking interval is adaptively obtained based on the intervals between a sequence of consecutive pointer adjustments in the received signal, i.e., the STS-1 signal. In one embodiment, the bit leaking interval estimate is obtained by employing a moving average of the intervals between the pointer adjustments. The desired bit leaking is effected by employing an accumulator which is responsive to the received pointer adjustments and a representation of the estimated bit leaking interval, in conjunction with a comparator. The accumulator output count is supplied to the comparator along with the current write address of the elastic store. Leak bits are supplied as an output from the comparator one at a time to the phase locked loop which, in turn, generates a smooth read clock for the elastic store.