公开(公告)号：US11573817B2

公开(公告)日：2023-02-07

申请号：US16934332

申请日：2020-07-21

申请人： VMware, Inc.

发明人： Eric Schkufza ,  Christopher J. Rossbach

IPC分类号： G06F9/455 ,  G06F30/331 ,  G06F30/323

摘要： Examples provide a method of virtualizing a hardware accelerator in a virtualized computing system. The virtualized computing system includes a hypervisor supporting execution of a plurality of virtual machines (VMs). The method includes: receiving a plurality of sub-programs at a compiler in the hypervisor from a plurality of compilers in the respective plurality of VMs, each of the sub-programs including a hardware-description language (HDL) description; combining, at the compiler in the hypervisor, the plurality of sub-programs into a monolithic program; generating, by the compiler in the hypervisor, a circuit implementation for the monolithic program, the circuit implementation including a plurality of sub-circuits for the respective plurality of sub-programs; and loading, by the compiler in the hypervisor, the circuit implementation to a programmable device of the hardware accelerator.

公开(公告)号：US11461520B1

公开(公告)日：2022-10-04

申请号：US17180239

申请日：2021-02-19

申请人： Cadence Design Systems, Inc.

发明人： Arvind Chokhani ,  Joseph Micahel Swenton ,  Santosh Subhaschandra Malagi

IPC分类号： G06F30/31 ,  G01R31/3183 ,  G06F30/343 ,  G06F30/323 ,  G06F30/333 ,  G06F30/367 ,  G06F30/398 ,  G06F30/3323

摘要： An integrated circuit (IC) test engine extracts an input to output propagation delay for each cell instance of each of a plurality of cell types in an IC design from an SDF file for the IC design. The IC test engine extracts a node slack of each cell instance of each of the plurality of cell types of the IC design from a node slack report. The IC test engine also generates cell-aware test patterns for each cell instance of each cell type in the IC design to test a fabricated IC chip that is based on the IC design for defects corresponding to a subset of a plurality of candidate defects characterized in the plurality of fault rules files. Each cell-aware test pattern is configured to sensitize and propagate a transition along the longest possible path to test small delay defects in cell instances of the fabricated IC chip.

公开(公告)号：US20220056868A1

公开(公告)日：2022-02-24

申请号：US17519629

申请日：2021-11-05

申请人： Energy Internet Corporation

发明人： Shankar Ramamurthy ,  Mohan J. Kumar

IPC分类号： F02G1/045 ,  F02G1/053 ,  G06F30/323

摘要： Disclosed techniques include control and configuration of software-defined machines. A hardware design for a mechanical system is obtained. The mechanical system includes a plurality of components that includes a liquid piston heat engine. Couplings between the plurality of components are described. A plurality of layers for the mechanical system is defined. The mechanical system that includes the liquid piston heat engine is implemented. The implementation is across the plurality of layers. The implementation is based on the couplings between the plurality of components. The couplings are described using connectivity maps. The implementation is based on construction rules. An application programming interface is used to communicate information on the plurality of layers for the mechanical system. The plurality of layers provides progressive levels of abstraction for the mechanical system.

公开(公告)号：US20210319159A1

公开(公告)日：2021-10-14

申请号：US16848530

申请日：2020-04-14

申请人： Cambridge Quantum Computing Limited

发明人： Alexander Cowtan ,  Ross William Duncan ,  William Victor Simmons

IPC分类号： G06F30/323 ,  G06N10/00 ,  G06F30/327

摘要： Concepts, systems and methods are described for generating a quantum circuit from a Unitary Coupled Cluster (UCC) ansatz which represents the excitation of a reference state by a parameterised operator including excitation operators. The UCC ansatz includes multi-qubit Pauli operators, referred to as Pauli strings, determined from each excitation operator. The method comprises partitioning the Pauli strings into mutually commuting sets and sequencing the Pauli strings by set. Pauli gadgets are then generated from the Pauli strings by Trotterization, the Pauli gadgets having the same sequencing by set as the Pauli strings. Each set of Pauli gadgets is diagonalised to convert the Pauli gadgets into phase gadgets which are then transformed into one- and two-qubit native gates to generate the quantum circuit.

公开(公告)号：US20210295169A1

公开(公告)日：2021-09-23

申请号：US17231866

申请日：2021-04-15

申请人： NVIDIA Corp.

发明人： Harbinder Sikka ,  Kaushik Narayanun ,  Lijuan Luo ,  Karthikeyan Natarajan ,  Manjunatha Gowda ,  Sandeep Gangundi

IPC分类号： G06N3/08 ,  G06T1/20 ,  G06T11/20 ,  G06N3/04 ,  G06F30/323

摘要： Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

公开(公告)号：US11055455B1

公开(公告)日：2021-07-06

申请号：US16788949

申请日：2020-02-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

发明人： Sandeep Kumar Goel ,  Yun-Han Lee ,  Ankita Patidar

IPC分类号： G06F30/323 ,  G06F30/3323 ,  G06F30/394 ,  G06F30/392 ,  G03F1/70 ,  G06F119/12

摘要： A method (of reducing errors in a migration a first netlist to a second netlist, the first and second netlists representing corresponding first and second implementations of a circuit design under corresponding first and second semiconductor process technology (SPT) nodes, at least the second netlist being stored on a non-transitory computer-readable medium), the method including: inspecting a timing constraint list for addition candidates, the timing constraint list corresponding to an initial netlist which represents the second implementation; relative to a logic equivalence check (LEC) context, increasing a number of comparison points based on the addition candidates, resulting in first version of the second netlist; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the first version of the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.

公开(公告)号：US20210192112A1

公开(公告)日：2021-06-24

申请号：US16788949

申请日：2020-02-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY, LIMITED

发明人： Sandeep Kumar GOEL ,  Yun-Han LEE ,  Ankita PATIDAR

IPC分类号： G06F30/323 ,  G06F30/3323 ,  G06F30/392 ,  G06F30/394 ,  G03F1/70

摘要： A method (of reducing errors in a migration a first netlist to a second netlist, the first and second netlists representing corresponding first and second implementations of a circuit design under corresponding first and second semiconductor process technology (SPT) nodes, at least the second netlist being stored on a non-transitory computer-readable medium), the method including: inspecting a timing constraint list for addition candidates, the timing constraint list corresponding to an initial netlist which represents the second implementation; relative to a logic equivalence check (LEC) context, increasing a number of comparison points based on the addition candidates, resulting in first version of the second netlist; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the first version of the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.

公开(公告)号：US20210097220A1

公开(公告)日：2021-04-01

申请号：US17035959

申请日：2020-09-29

申请人： University of Florida Research Foundation, Incorporated

发明人： Swarup Bhunia ,  Prabuddha Chakraborty ,  Abhiskek A. Nair ,  Tamzidul Hoque ,  Jonathan W. Cruz ,  Naren Masna ,  Pravin Gaikwad

IPC分类号： G06F30/323 ,  G06F30/398 ,  G06N20/00 ,  G06F21/55

摘要： Embodiments of the present disclosure provide methods, apparatus, and computer program products for generating an insertion netlist for a target circuit configured for inserting a malicious design alteration into the circuit based on a design identifying reference trigger nets. Features are extracted for each net identified in a netlist for the circuit. A set of reference trigger features is generated for each of the reference trigger nets. A net is selected from the netlist for each set of reference trigger features based on a similarity between the features of the net and the set of reference trigger features. The insertion netlist is generated that includes the circuit with the malicious design alteration inserted at each of the selected nets.

公开(公告)号：US10915573B2

公开(公告)日：2021-02-09

申请号：US16129855

申请日：2018-09-13

申请人： International Business Machines Corporation

发明人： Addis Armenta Lopez ,  Jesus Gabriel Trillo Vargas ,  Jose de Jesus Jimenez Gonzalez ,  Alejandro M. Lopez ,  Adolfo Mendez Morales

IPC分类号： G06F30/30 ,  G06F30/323 ,  G06F30/33 ,  G06F30/3323 ,  G06F16/583 ,  G06F17/11 ,  G06F16/56

摘要： A cognitive, artificially intelligent system employs, in part, visual recognition and image processing to transform electronic design information, such as a schematic diagram, into a machine-readable data structure suitable for machine-based comparison of one data structure against another data structure of like kind. A comparison method identifies and quantifies similarities or equivalencies between the any such data structures, and hence between respectively corresponding electronic designs.

公开(公告)号：US20240362392A1

公开(公告)日：2024-10-31

申请号：US18769843

申请日：2024-07-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Wei Chung ,  Tung-Heng Hsieh ,  Chung-Hui Chen ,  Chung-Yi Lin

IPC分类号： G06F30/392 ,  G06F30/323 ,  G06F30/398 ,  G06F111/20

CPC分类号： G06F30/392 ,  G06F30/323 ,  G06F30/398 ,  G06F2111/20

摘要： An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.