-
公开(公告)号：US11727177B2
公开(公告)日：2023-08-15
申请号：US17836954
申请日：2022-06-09
发明人： Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
IPC分类号： G06F30/327 , G06F30/398 , G06F30/333 , G06F30/3308 , G06F119/18 , G06F119/02
CPC分类号： G06F30/327 , G06F30/398 , G06F30/333 , G06F30/3308 , G06F2119/02 , G06F2119/18
摘要： A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a unique dominant feature among a plurality of features of the plurality of paths. The dominant feature of a group among the plurality of groups is slack. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.
-
公开(公告)号：US11699010B2
公开(公告)日：2023-07-11
申请号：US17365468
申请日：2021-07-01
发明人： Sandeep Kumar Goel , Ankita Patidar , Yun-Han Lee
IPC分类号： G06F30/323 , G06F30/3323 , G06F30/392 , G06F30/394 , G03F1/70 , G06F119/12
CPC分类号： G06F30/323 , G03F1/70 , G06F30/3323 , G06F30/392 , G06F30/394 , G06F2119/12
摘要： A method of manufacturing a semiconductor device includes reducing errors in a migration of a first netlist to a second netlist, the first netlist corresponding to a first semiconductor process technology (SPT), the second first netlist corresponding to a second SPT, the first and second netlists each representing a same circuit design, the reducing errors including: inspecting a timing constraint list corresponding to the second netlist for addition candidates; generating a first version of the second netlist having a first number of comparison points relative to a logic equivalence check (LEC) context, the first number of comparison points being based on the addition candidates; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.
-
公开(公告)号：US11879933B2
公开(公告)日：2024-01-23
申请号：US17393232
申请日：2021-08-03
发明人： Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
IPC分类号： G01R31/02 , G06F30/398 , G01R31/317 , G06F119/08 , G01R31/28
CPC分类号： G01R31/2855 , G01R31/31721 , G06F30/398 , G06F2119/08
摘要： A method of testing an integrated circuit on a test circuit board includes performing, by a processor, a simulation of a first heat distribution throughout an integrated circuit design, manufacturing the integrated circuit according to the integrated circuit design, and simultaneously performing a burn-in test of the integrated circuit and an automated test of the integrated circuit. The burn-in test has a minimum burn-in temperature of the integrated circuit and a burn-in heat distribution across the integrated circuit. The integrated circuit design corresponds to the integrated circuit. The integrated circuit is coupled to the test circuit board. The integrated circuit includes a set of circuit blocks and a first set of heaters.
-
公开(公告)号：US11055455B1
公开(公告)日：2021-07-06
申请号：US16788949
申请日：2020-02-12
发明人： Sandeep Kumar Goel , Yun-Han Lee , Ankita Patidar
IPC分类号： G06F30/323 , G06F30/3323 , G06F30/394 , G06F30/392 , G03F1/70 , G06F119/12
摘要： A method (of reducing errors in a migration a first netlist to a second netlist, the first and second netlists representing corresponding first and second implementations of a circuit design under corresponding first and second semiconductor process technology (SPT) nodes, at least the second netlist being stored on a non-transitory computer-readable medium), the method including: inspecting a timing constraint list for addition candidates, the timing constraint list corresponding to an initial netlist which represents the second implementation; relative to a logic equivalence check (LEC) context, increasing a number of comparison points based on the addition candidates, resulting in first version of the second netlist; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the first version of the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.
-
公开(公告)号：US11837308B2
公开(公告)日：2023-12-05
申请号：US17713904
申请日：2022-04-05
发明人： Ankita Patidar , Sandeep Kumar Goel
IPC分类号： G01R31/28 , G11C29/44 , G11C29/12 , G11C29/10 , G11C29/02 , G11C29/50 , G01R31/3185 , G01R31/3183 , G06F11/07 , G01R31/3181
CPC分类号： G11C29/44 , G01R31/318342 , G01R31/318547 , G11C29/02 , G11C29/10 , G11C29/12005 , G11C29/50004 , G01R31/2837 , G01R31/31813 , G06F11/079
摘要： A method of identifying cell-internal defects: obtaining a circuit design of an integrated circuit, the circuit design including netlists of one or more cells coupled to one another; identifying the netlist corresponding to one of the one or more cells; injecting a defect to one of a plurality of circuit elements and one or more interconnects of the cell; retrieving a first current waveform at a location of the cell where the defect is injected by applying excitations to inputs of the cell; retrieving, without the defect injected, a second current waveform at the location of the cell by applying the same excitations to the inputs of the cell; and selectively annotating, based on the first current waveform and the second current waveform, an input/output table of the cell with the defect.
-
公开(公告)号：US20230385498A1
公开(公告)日：2023-11-30
申请号：US18303219
申请日：2023-04-19
发明人： Sandeep Kumar Goel , Ankita Patidar
IPC分类号： G06F30/333 , G06F30/33 , G06F30/39 , G06F30/392
CPC分类号： G06F30/333 , G06F30/392 , G06F30/39 , G06F30/33
摘要： Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.
-
公开(公告)号：US11343433B2
公开(公告)日：2022-05-24
申请号：US16595088
申请日：2019-10-07
发明人： Sandeep Kumar Goel , Yun-Han Lee , Ashok Mehta
摘要： An apparatus includes an image sensor having a light sensing region, the light sensing region being partitioned into a plurality of sub-regions, a first sub-region of the plurality of sub-regions has a first size, a second sub-region of the plurality of sub-regions has a second size different from the first size, and the second sub-region partially overlaps with the first sub-region. The apparatus further includes a processor coupled with the image sensor, wherein the processor includes a plurality of pixel processing units, and each processing unit of the plurality of processing units is configured to generate a processed image based on an image captured by a corresponding sub-region of the plurality of sub-regions. The apparatus further includes a plurality of lenses configured to focus incident light onto the image sensor.
-
公开(公告)号：US09513332B2
公开(公告)日：2016-12-06
申请号：US14459801
申请日：2014-08-14
发明人： Sandeep Kumar Goel , Mill-Jer Wang
IPC分类号： G01R31/00 , G01R31/28 , G01R1/04 , G01R1/073 , G01R31/319
CPC分类号： G01R31/2889 , G01R1/0408 , G01R1/07342 , G01R31/31908
摘要： A method of testing an integrated circuit die comprises partitioning a first probe card partition layout of the integrated circuit die having one or more sections comprising a first quantity of section types into a second probe card partition layout having a greater quantity of sections comprising a second quantity of section types, the second quantity of section types being less than the first quantity of section types. The method also comprises using one or more probe cards to test the sections in the second probe card partition layout, each of the one or more probe cards having a test contact pattern that corresponds with a test contact pattern of one of each section type included in the second probe card partition layout.
摘要翻译： 一种测试集成电路管芯的方法包括将具有一个或多个部分的集成电路管芯的第一探针卡分隔布局分成包括第一数量的部分类型到具有更大数量的部分的第二探针卡分配布局，所述部分包括第二数量 的截面类型，第二数量的截面类型小于第一数量的截面类型。 该方法还包括使用一个或多个探针卡来测试第二探针卡分区布局中的部分，所述一个或多个探针卡中的每一个具有与包括在每个部分类型之一的测试接触图案相对应的测试接触图案 第二个探针卡分区布局。
-
公开(公告)号：US20150058819A1
公开(公告)日：2015-02-26
申请号：US14087650
申请日：2013-11-22
发明人： Sandeep Kumar Goel , Ashok Mehta
CPC分类号： G06F17/5081 , G01R31/2818 , G01R31/2851 , G01R31/2853 , G01R31/318513 , G06F17/5077 , G06F2217/14 , G06F2217/40 , H01L22/00 , H01L22/14 , H01L23/49816 , H01L23/49827 , H01L23/49844 , H01L24/02 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/02331 , H01L2224/02375 , H01L2224/02379 , H01L2224/02381 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2224/81192 , H01L2924/014 , H01L2924/00014 , H01L2924/01029 , H01L2924/01014 , H01L2924/01047 , H01L2924/01011 , H01L2924/00012
摘要： Provided is a method of assigning a first set of probe pads to an interposer for maximizing a defect coverage for the interposer. The interposer includes a second set of nets and the defect coverage is based on a ratio between a tested net length and an overall net length. The method includes processing the second set such that every net interconnecting more than two micro-bumps is divided into a plurality of nets and every two of the more than two micro-bumps are interconnected by one of the plurality of nets. The method further includes calculating an untested length of each net in the second set; selecting a first net from the second set with the maximum untested length; selecting two probe pads from the first set based on a user-defined cost function; and connecting the two probe pads to the first net with two dummy nets.
摘要翻译： 提供了一种将第一组探针焊盘分配给插入器以最大化插入器的缺陷覆盖的方法。 插入器包括第二组网络，并且缺陷覆盖范围基于被测净长度与总净长度之间的比率。 该方法包括处理第二组，使得互连多于两个微凸块的每个网络被分成多个网络，并且多于两个微凸块中的每两个通过多个网络中的一个互连。 该方法还包括计算第二组中每个网络的未测试长度; 从第二组中选择具有最大未测试长度的第一个网络; 基于用户定义的成本函数从第一组中选择两个探针焊盘; 并将两个探针焊盘连接到具有两个虚拟网络的第一个网络。
-
10.发明授权Reducing design verification time while maximizing system functional coverage 有权减少设计验证时间，同时最大化系统功能覆盖公开(公告)号：US08826202B1
公开(公告)日：2014-09-02
申请号：US13890732
申请日：2013-05-09
发明人： Sandeep Kumar Goel , Ashok Mehta
CPC分类号： G06F11/263 , G06F17/504
摘要： A system for functional verification of a chip design includes the chip design, a test generator, a test bench, a verification tool, and a coverage tool. The coverage tool is configured to receive chip design, user input, and coverage files from the verification tool to generate information for the test generator to improve the test coverage of the verification tool. The method includes receiving a chip design, functionally testing the chip design, generating coverage files, receiving user options, including a coverage basis, a report basis, and a defined coverage, calculating coverage impact and new overall coverage using the defined coverage and coverage files, and ranking each report basis according to coverage impact of each coverage basis.
摘要翻译： 用于芯片设计功能验证的系统包括芯片设计，测试发生器，测试台，验证工具和覆盖工具。 覆盖工具被配置为从验证工具接收芯片设计，用户输入和覆盖文件，以生成测试发生器的信息，以提高验证工具的测试覆盖率。 该方法包括接收芯片设计，功能测试芯片设计，生成覆盖文件，接收用户选项，包括覆盖基础，报告基础和定义的覆盖范围，使用定义的覆盖和覆盖文件计算覆盖影响和新的整体覆盖 并根据每个覆盖范围的覆盖面影响对每个报告进行排序。
-
-
-
-
-
-
-
-
-
搜索结果
59 条记录 (耗时 0.032 秒)
