-
公开(公告)号：US20230229887A1
公开(公告)日：2023-07-20
申请号：US18123918
申请日：2023-03-20
发明人： Farnood Merrikh BAYAT , Xinjie GUO , Dmitri STRUKOV , Nhan DO , Hieu Van TRAN , Vipin TIWARI , Mark REITEN
IPC分类号： G06N3/04 , G06N3/063 , G11C11/54 , G11C16/34 , G11C29/38 , G06N3/045 , G11C16/08 , G11C16/12 , G11C16/16 , G06F3/06
CPC分类号： G06N3/04 , G06N3/063 , G11C11/54 , G11C16/3436 , G11C29/38 , G06N3/045 , G11C16/08 , G11C16/12 , G11C16/16 , G06F3/061 , G06F3/0655 , G06F3/0688
摘要： Numerous examples are disclosed for an output block coupled to a non-volatile memory array in a neural network and associated methods. In one example, a circuit for converting a current in a neural network into an output voltage comprises a non-volatile memory cell comprises a word line terminal, a bit line terminal, and a source line terminal, wherein the bit line terminal receives the current; and a switch for selectively coupling the word line terminal to the bit line terminal; wherein when the switch is closed, the current flows into the non-volatile memory cell and the output voltage is provided on the bit line terminal.
-
公开(公告)号：US20230223082A1
公开(公告)日：2023-07-13
申请号：US17955733
申请日：2022-09-29
发明人： Myoung-Ho SON , Doo-Yeun JUNG , Sung-Kwan JUNG
CPC分类号： G11C16/08 , G11C16/16 , G11C29/12 , G11C16/0483
摘要： An operating method of a memory device includes: acquiring an address of a first bad word line, the first bad word line included in a plurality of word lines of the memory device; detecting whether word lines adjacent to the first bad word line are bad based on the address of the first bad word line, the word lines adjacent to the first bad word line included in the plurality of word lines; designating a first word line among the word lines adjacent to the first bad word line as a prohibited word line, the first word line being detected as a second bad word line; and sending first data via a second word line among the word lines adjacent to the first bad word line, the second word line being detected as a normal word line.
-
公开(公告)号：US11699490B2
公开(公告)日：2023-07-11
申请号：US17220218
申请日：2021-04-01
发明人： Soyeong Gwak , Raeyoung Lee , Jinkyu Kang , Sejun Park , Changhwan Shin , Jaeduk Lee , Woojae Jang
CPC分类号： G11C16/16 , G11C7/106 , G11C7/1087 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/349
摘要： An operating method of a storage device includes reading a wear-out pattern of a memory block when a controller determines the memory block is a re-use memory block of a non-volatile memory device; selecting an operation mode corresponding to the read wear-out pattern using the controller; and transmitting the selected operation mode to the non-volatile memory device using the controller.
-
64.发明公开公开(公告)号：US20230207644A1
公开(公告)日：2023-06-29
申请号：US17968037
申请日：2022-10-18
发明人： Young-Joo JEON , Byung Joo Go , Hee-Sung Kam , Su Jin Park
IPC分类号： H01L29/417 , H01L27/11519 , H01L27/11524 , H01L27/11529 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L23/522 , H01L23/528 , G11C16/04 , G11C16/26 , G11C16/16
CPC分类号： H01L29/41775 , G11C16/16 , G11C16/26 , G11C16/0483 , H01L23/5226 , H01L23/5283 , H01L27/1157 , H01L27/11519 , H01L27/11524 , H01L27/11529 , H01L27/11565 , H01L27/11573
摘要： A semiconductor device includes: a substrate includes an active area; a gate structure intersecting the active area; a source/drain area disposed on the active area, a lower contact disposed on the source/drain area or the gate structure; an upper contact disposed on the lower contact; and a plurality of conductive lines disposed on the upper contact, wherein the plurality of conductive lines extend in a first direction parallel to an upper surface of the substrate, wherein the plurality of conductive lines includes a first conductive line disposed on the upper contact, wherein a size in the first direction of the lower contact is smaller than a size in the first direction of the upper contact, wherein a size in a second direction of the lower contact is greater than a size in the second direction of the upper contact, wherein the second direction intersects the first direction.
-
65.发明公开公开(公告)号：US20230186998A1
公开(公告)日：2023-06-15
申请号：US17551640
申请日：2021-12-15
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/16 , G11C16/32 , G11C16/3404
摘要： A memory apparatus and method of operation are provided. The memory apparatus includes memory cells configured to retain a threshold voltage. The memory cells are connected to one of a plurality of word lines and are arranged in strings comprising a plurality of blocks. A control means is coupled to the plurality of word lines and the strings and is configured to periodically determine a read frequency metric associated with a plurality of read operations of one of the plurality of blocks of the memory cells. The control means is also configured to relocate data of the one of the plurality of blocks and cause the one of the plurality of blocks to remain unused for a predetermined relaxation time based on the read frequency metric.
-
公开(公告)号：US20230162808A1
公开(公告)日：2023-05-25
申请号：US17534832
申请日：2021-11-24
发明人： Michael IONIN , Lior AVITAL , Tomer T. ELIASH , Lola GRIN , Alexander BAZARSKY , Itay BUSNACH , Lior BUBLIL , Mahim GUPTA
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/3404 , G11C16/26
摘要： A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a power loss event has occurred, determine that one or more blocks are in an erased state, examine a block of the one or more blocks to determine whether the block is a SLC erased block or a TLC erased block, and place the block in a SLC pre-erase heap if the block is the SLC erased block or in a TLC pre-erase heap if the block is the TLC erased block. The controller is further configured to determine a first bit count of page0 for a SLC voltage for the block, determine a second bit count of page1 for a TLC voltage for the block, and classify the block as either a SLC erased block or a TLC erased block.
-
公开(公告)号：US20230162800A1
公开(公告)日：2023-05-25
申请号：US17560488
申请日：2021-12-23
发明人： Tse-Yen LIU
CPC分类号： G11C16/16 , G11C16/102 , G11C16/32 , H03K19/20
摘要： A memory device includes a main memory, a first sub-memory and a controller. When the first sub-memory is erased, the first sub-memory generates a first erase completion signal. The controller receives an erase signal to erase the main memory. The controller performs an erase operation on the main memory according to the erase signal and the first erase completion signal.
-
公开(公告)号：US20230154550A1
公开(公告)日：2023-05-18
申请号：US17529722
申请日：2021-11-18
发明人： Jiacen Guo , Xiang Yang , Abhijith Prakash
CPC分类号： G11C16/3445 , G11C16/3404 , G11C16/16 , G11C16/28 , G11C16/08 , G11C16/0433
摘要： A method of erasing memory cells in a memory device is provided. The method includes grouping a plurality of word lines into a first group, which does not include edge word lines, and a second group, which does include edge word lines. An erase operation is performed on the memory cells of the first and second groups until erase-verify of the memory cells of the first group passes. It is then determined if further erase of the memory cells of the second group is necessary. In response to it being determined that the additional erase operation is necessary, an additional erase operation is performed on at least some of the memory cells of the second group until erase-verify of the memory cells of the second group passes.
-
69.发明申请公开(公告)号：US20230128347A1
公开(公告)日：2023-04-27
申请号：US17715809
申请日：2022-04-07
发明人： Honam YOO , Jong-Ho LEE
摘要： A flash memory device includes a cell array and a control circuit. The cell array includes a first NAND string having first flash memory cells having control gates respectively connected to word lines, and a first bit line selection switch connecting the first flash memory cells to a first bit line according to a control of a first string selection line. The control circuit controls a first erase operation for erasing a selected flash memory cell. The control circuit controls a voltage difference between the first bit line and the first string selection line to have a first value for generating gate induced drain leakage (GIDL) at the first bit line selection switch, and controls a voltage of a control gate of the selected flash memory cell and a voltage of a control gate of an unselected flash memory cell to be different from each other.
-
公开(公告)号：US20230125101A1
公开(公告)日：2023-04-27
申请号：US18088046
申请日：2022-12-23
发明人： KWANGHO CHOI , JIN-YOUNG KIM , SE HWAN PARK , IL HAN PARK , JI-SANG LEE , JOONSUC JANG
IPC分类号： G11C16/34 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/24 , H01L25/065 , H01L25/18 , H01L23/00
摘要： A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.
-
-
-
-
-
-
-
-
-
搜索结果
3033 条记录 (耗时 0.032 秒)
