公开(公告)号：US20150052332A1

公开(公告)日：2015-02-19

申请号：US13968844

申请日：2013-08-16

Applicant: Mikael Mortensen

Inventor： Mikael Mortensen

IPC: G06F9/24

CPC classification number: G06F9/3879 ,  G06F9/3877 ,  G06F15/7889

Abstract: A microprocessor circuit may include a software programmable microprocessor core and a data memory accessible via a data memory bus. The data memory may include sets of configuration data structured according to respective predetermined data structure specifications for configurable math hardware accelerators, and sets of input data for configurable math hardware accelerators, each configured to apply a predetermined signal processing function to the set of input data according to received configuration data. A configuration controller is coupled to the data memory via the data memory bus and to the configurable math hardware accelerators. The configuration controller may fetch the configuration data for each math hardware accelerator from the data memory and translate the configuration data. The configuration controller may transmit each set of configuration data to the corresponding configurable math hardware accelerator and write the configuration data to configuration registers of the math hardware accelerator.

Abstract translation: 微处理器电路可以包括可通过数据存储器总线访问的软件可编程微处理器核心和数据存储器。 数据存储器可以包括根据用于可配置数学硬件加速器的各个预定数据结构规范而构成的配置数据集合，以及用于可配置数学硬件加速器的输入数据集合，每个配置数据硬件加速器被配置为根据输入数据集应用预定信号处理功能 接收配置数据。 配置控制器经由数据存储器总线和可配置的数学硬件加速器耦合到数据存储器。 配置控制器可以从数据存储器获取每个数学硬件加速器的配置数据，并转换配置数据。 配置控制器可以将每组配置数据发送到相应的可配置数学硬件加速器，并将配置数据写入数学硬件加速器的配置寄存器。

公开(公告)号：US20150042501A1

公开(公告)日：2015-02-12

申请号：US14524729

申请日：2014-10-27

Applicant: Hajime SHIBATA

Inventor： Hajime SHIBATA

IPC: H03M1/44 ,  H03M1/12 ,  H03M1/00

CPC classification number: H03M1/44 ,  H03M1/001 ,  H03M1/002 ,  H03M1/124 ,  H03M1/1245 ,  H03M1/167

Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

Abstract translation: A转换器可以包括串联连接的多个转换器级。 每个转换器级可以接收时钟信号和模拟输入信号，并且可以产生模拟输出信号和数字输出信号。 每个转换器级可以包括产生数字输出信号的编码器，产生重构信号的解码器，产生延迟信号的延迟转换器和产生残差信号的放大器，其中延迟信号可以是连续电流信号。

公开(公告)号：US08948326B2

公开(公告)日：2015-02-03

申请号：US13844759

申请日：2013-03-15

Applicant: Analog Devices Technology

Inventor： Haim Primo ,  Yosef Stein

IPC: H04B14/06 ,  H04L25/03 ,  H03D3/00 ,  H03D7/16 ,  H04L27/38

CPC classification number: H04L25/03006 ,  H03D3/009 ,  H03D7/165 ,  H03D2200/0054 ,  H04B1/30 ,  H04L27/3863

Abstract: An electrical circuit includes a local oscillator configured to generate a first reference signal and a second reference signal having a predetermined phase shift with the first reference signal, an I-channel mixer configured to inject the first reference signal to an incoming signal and generate a first output, a compensation mixer configured to multiply the first output with a constant factor to generate a second output, a first low pass filter configured to approximately attenuate frequencies in the second output to generate a third output, and a first correcting filter configured to filter the third output to generate a fourth output. The first correcting filter is configured to reduce a channel impulse response mismatch between the first low pass filter and a second low pass filter, which is configured to attenuate frequencies in a Q-channel of the incoming signal. In specific embodiments, the phase shift includes 45°.

Abstract translation: 电路包括配置成产生第一参考信号的本地振荡器和具有与第一参考信号相关的预定相移的第二参考信号，配置为将第一参考信号注入到输入信号并产生第一参考信号的I信道混合器 输出，配置为将第一输出与常数因子相乘以产生第二输出的补偿混合器，被配置为近似地衰减第二输出中的频率以产生第三输出的第一低通滤波器，以及第一校正滤波器， 第三输出产生第四输出。 第一校正滤波器被配置为减少第一低通滤波器和第二低通滤波器之间的信道脉冲响应失配，其被配置为衰减输入信号的Q信道中的频率。 在具体实施例中，相移包括45°。

公开(公告)号：US08947148B2

公开(公告)日：2015-02-03

申请号：US14162297

申请日：2014-01-23

Applicant: Analog Devices Technology

Inventor： Kareem Atout

IPC: H03K3/00 ,  H03K3/011

CPC classification number: H03K3/011 ,  H02M3/157 ,  H02M2001/008

Abstract: In one example, there is disclosed a hybrid analog-digital point-of-load controller (ADPOL) for use in a power supply. The ADPOL is configured to respond to transient current loads. In the presence of moderate current transients, power is clocked by a digital power core, which may be programmatically configured to adjust pulse width in response to the transient. In the presence of larger current transients, control may be passed to an analog transient compensator, which includes high-speed circuitry selecting between a very high-duty-cycle clock and a very low-duty-cycle clock, which will drive the transient back to the digital control domain.

Abstract translation: 在一个示例中，公开了一种用于电源的混合模拟 - 数字点负载控制器（ADPOL）。 ADPOL配置为响应瞬态电流负载。 在存在中等电流瞬变的情况下，功率由数字电源核心计时，数字电源核心可以被编程配置为响应于瞬态来调整脉冲宽度。 在存在较大的电流瞬变的情况下，可以将控制传递到模拟瞬态补偿器，其包括在非常高占空比时钟和非常低占空比时钟之间的高速电路选择，这将驱动瞬态回 到数字控制领域。

公开(公告)号：US08941368B2

公开(公告)日：2015-01-27

申请号：US13789210

申请日：2013-03-07

Applicant: Analog Devices Technology

Inventor： Shanshan Yang ,  Guoming Wu ,  Bin Shao

IPC: G05F1/40 ,  G05F1/46

CPC classification number: G05F1/46 ,  H02M1/36 ,  H02M3/158 ,  H02M2001/0032 ,  Y02B70/16

Abstract: A method and system to inhibit the switching of a current mode switching converter having high and low side switching elements coupled to an output inductor, the other end of which is coupled to an output node, and operated with respective modulated switching signals to regulate an output voltage Vout produced at the node. A current IC that varies with the difference between a reference voltage and a voltage proportional to Vout is compared with and a current IDETECT—PEAK which varies with the current conducted by the high side switching element; the result of the comparison of IC and IDETECT—PEAK is used to control the regulation of Vout during normal operation. Current IC is also compared with a current IDETECT—VALLEY which varies with the current conducted by the low side switching element. When IDETECT—VALLEY>IC, a ‘skip mode’ is triggered during which the switching signals are inhibited.

Abstract translation: 一种抑制具有耦合到输出电感器的高低侧开关元件的电流模式切换转换器的方法和系统，该输出电感器的另一端耦合到输出节点，并且用相应的调制开关信号进行操作，以调节输出 在节点处产生的电压Vout。 与参考电压和与Vout成比例的电压之间的差异变化的电流IC与当前由高侧开关元件传导的电流变化的IDETECT-PEAK进行比较; IC和IDETECT-PEAK的比较结果用于控制正常工作期间Vout的调节。 电流IC还与当前的IDETECT-VALLEY进行比较，其随着低侧开关元件所传导的电流而变化。 当IDETECT-VALLEY> IC时，触发切换信号的“跳过模式”。

公开(公告)号：US08937467B2

公开(公告)日：2015-01-20

申请号：US13791210

申请日：2013-03-08

Applicant: Analog Devices Technology

Inventor： Song Qin

IPC: G05F1/40 ,  G05F3/02

CPC classification number: H02M3/158 ,  H02M2001/0009

Abstract: Apparatus and methods for current sensing in switching regulators are provided. In certain implementations, a switching regulator includes a switch transistor, a replica transistor, a sense resistor, and a current sensing circuit. The drain and gate of the switch transistor can be electrically connected to the drain and gate of the replica transistor, respectively. The current sensing circuit can generate an output current that varies in response to a sense current from a source of the replica transistor. Additionally, the current sensing circuit can sink the sense current when the sense current flows from the drain to the source of the replica transistor and source the sense current when the sense current flows from the source to the drain of the replica transistor. The sense resistor can receive the output current such that the voltage across the sense resistor changes in relation to the current through the switch transistor.

Abstract translation: 提供了开关稳压器中电流检测的装置和方法。 在某些实施方案中，开关调节器包括开关晶体管，复制晶体管，检测电阻器和电流感测电路。 开关晶体管的漏极和栅极可以分别电连接到复制晶体管的漏极和栅极。 电流感测电路可以产生响应于来自复制晶体管的源的感测电流而变化的输出电流。 此外，当感测电流从复制晶体管的漏极流到源极时，电流感测电路可以吸收感测电流，并且当感测电流从复制晶体管的源极流到漏极时，该电流感测电路能够输出感测电流。 检测电阻器可以接收输出电流，使得检测电阻两端的电压相对于通过开关晶体管的电流而变化。

公开(公告)号：US08928303B2

公开(公告)日：2015-01-06

申请号：US13827666

申请日：2013-03-14

Applicant: Analog Devices Technology

Inventor： Zhijie Zhu ,  Junxiao Chen ,  Bin Shao

IPC: H02M3/156

CPC classification number: H02M3/156 ,  H02M2003/1566

Abstract: Apparatus and methods for generating a drive signal of a switching signal are disclosed. A first circuit receives an oscillating reference signal, a first compensation signal, a second compensation signal, and a third compensation signal. The first compensation signal is indicative of an error between an output voltage of a power converter and a reference voltage. The second compensation signal is indicative of the error relative to a threshold. The third compensation signal is indicative of an output current of the power converter. The first circuit generates a comparison signal having a waveform including pulses having durations based at least partly on a combination of the periodic reference signal, the first compensation signal, the second compensation signal, and the third compensation signal. A second circuit receives a clock signal and the comparison signal and generates a drive signal for activation and deactivation of a driver transistor.

Abstract translation: 公开了用于产生开关信号的驱动信号的装置和方法。 第一电路接收振荡参考信号，第一补偿信号，第二补偿信号和第三补偿信号。 第一补偿信号表示功率转换器的输出电压与参考电压之间的误差。 第二补偿信号指示相对于阈值的误差。 第三补偿信号表示功率转换器的输出电流。 第一电路产生具有波形的比较信号，该波形包括至少部分地基于周期性参考信号，第一补偿信号，第二补偿信号和第三补偿信号的组合的具有持续时间的脉冲。 第二电路接收时钟信号和比较信号并产生用于驱动晶体管的激活和去激活的驱动信号。

公开(公告)号：US20140365548A1

公开(公告)日：2014-12-11

申请号：US13914731

申请日：2013-06-11

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Mikael Mortensen

IPC: G06F7/57

CPC classification number: G06F17/16 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3824 ,  G06F9/3893

Abstract: In at least one example embodiment, a microprocessor circuit is provided that includes a microprocessor core coupled to a data memory via a data memory bus comprising a predetermined integer number of data wires (J); the single-ported data memory configured for storage of vector input elements of an N element vector in a predetermined vector element order and storage of matrix input elements of an M×N matrix comprising M columns of matrix input elements and N rows of matrix input elements; a vector matrix product accelerator comprising a datapath configured for multiplying the N element vector and the matrix to compute an M element result vector, the vector matrix product accelerator comprising: an input/output port interfacing the data memory bus to the vector matrix product accelerator; a plurality of vector input registers for storage respective input vector elements received through the input/output port.

Abstract translation: 在至少一个示例性实施例中，提供了微处理器电路，其包括经由包括预定整数数据线（J）的数据存储器总线耦合到数据存储器的微处理器核心; 单端口数据存储器，其被配置为以预定向量元素顺序存储N个元素向量的向量输入元素，并存储包括M列矩阵输入元素和N行矩阵输入元素的M×N矩阵的矩阵输入元素 ; 矢量矩阵乘积加速器，其包括被配置为将所述N个元素向量和所述矩阵相乘以计算M元素结果向量的数据路径，所述向量矩阵乘积加速器包括：将所述数据存储器总线连接到所述向量矩阵乘积加速器的输入/输出端口; 多个向量输入寄存器，用于存储通过输入/输出端口接收的各个输入向量元素。

公开(公告)号：US08896475B2

公开(公告)日：2014-11-25

申请号：US13869454

申请日：2013-04-24

Applicant: Hajime Shibata

Inventor： Hajime Shibata

IPC: H03M1/38 ,  H03M1/00

CPC classification number: H03M1/44 ,  H03M1/001 ,  H03M1/002 ,  H03M1/124 ,  H03M1/1245 ,  H03M1/167

Abstract: A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

Abstract translation: A转换器可以包括串联连接的多个转换器级。 每个转换器级可以接收时钟信号和模拟输入信号，并且可以产生模拟输出信号和数字输出信号。 每个转换器级可以包括产生数字输出信号的编码器，产生重构信号的解码器，产生延迟信号的延迟转换器和产生残差信号的放大器，其中延迟信号可以是连续电流信号。

公开(公告)号：US20140339601A1

公开(公告)日：2014-11-20

申请号：US13896123

申请日：2013-05-16

Applicant: Analog Devices Technology

Inventor： Javier Alejandro Salcedo ,  David J. Clarke ,  Jonathan Glen Pfeifer

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L21/761 ,  H01L27/027 ,  H01L27/0817 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66121 ,  H01L29/7436 ,  H01L29/87

Abstract: Dual-tub junction-isolated voltage clamp devices and methods of forming the same are provided herein. The voltage clamp device can provide junction-isolated protection to low voltage circuitry connected between first and second high voltage interface pins. In certain implementations, a voltage clamp device includes a PNPN protection structure disposed in a p-well, a PN diode protection structure disposed in an n-well positioned adjacent the p-well, a p-type tub surrounding the p-well and the n-well, and an n-type tub surrounding the p-type tub. The p-type tub and the n-type tub provide junction isolation, the p-type tub can be electrically floating, and the n-type tub can be electrically connected to the second pin. The first and second pins can operate at a voltage difference below the junction isolation breakdown, and the second pin can operate with higher voltage than the first pin.

Abstract translation: 双槽结隔离电压钳装置及其形成方法在此提供。 电压钳位器件可以为连接在第一和第二高压接口引脚之间的低压电路提供结隔离保护。 在某些实施方式中，电压钳位装置包括设置在p阱中的PNPN保护结构，PN二极管保护结构，其布置在邻近p阱的n阱中，围绕p阱的p型阱和 n型井和围绕p型桶的n型桶。 p型桶和n型桶提供结隔离，p型桶可以电浮动，并且n型桶可以电连接到第二销。 第一和第二引脚可以在低于结隔离击穿的电压差下工作，而第二引脚可以以比第一引脚更高的电压工作。