公开(公告)号：US10542279B2

公开(公告)日：2020-01-21

申请号：US15714808

申请日：2017-09-25

Applicant: Intel Corporation

Inventor： Fangwen Fu ,  Jill M. Boyce

IPC: H04N19/52 ,  H04N19/105 ,  H04N19/70 ,  H04N19/82

Abstract: Temporal motion vector prediction control is described in video coding. In one example, a method includes receiving a plurality of frames representing encoded video, parsing an uncompressed header for each frame, determining whether a temporal motion vector prediction command is included within the parsed uncompressed header of a first frame, selecting a reference frame from a reference list of frames, retrieving motion vector information from the selected reference frame, performing temporal motion vector prediction on the first frame corresponding to the parsed uncompressed header if a temporal motion vector prediction command is included within the parsed header to form a motion predicted frame, applying a loop filter to the motion predicted frame, and rendering the frame as decoded video.

公开(公告)号：US10542243B2

公开(公告)日：2020-01-21

申请号：US15949191

申请日：2018-04-10

Applicant: Intel Corporation

Inventor： Evgeny Krestyannikov ,  Dmytro Paliy

IPC: H04N9/73 ,  H04N5/235 ,  H04N9/31 ,  H04N9/68

Abstract: A system, article, and method to perform light source estimation for image processing includes measuring a compactness of the distribution of the image data to select a light source.

公开(公告)号：US10535770B2

公开(公告)日：2020-01-14

申请号：US15505558

申请日：2014-09-24

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Rafael Rios ,  Kelin J. Kuhn ,  Ian A. Young ,  Justin R. Weber

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  B82Y10/00 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/66

Abstract: Described is a TFET comprising: a nanowire having doped regions for forming source and drain regions, and an un-doped region for coupling to a gate region; and a first termination material formed over the nanowire; and a second termination material formed over a section of the nanowire overlapping the gate and source regions. Described is another TFET comprising: a first section of a nanowire having doped regions for forming source and drain regions, and an undoped region for coupling to a gate region; a second section of the nanowire extending orthogonal to the first section, the second section formed next to the gate and source regions; and a termination material formed over the first and second sections of the nanowire.

公开(公告)号：US10516891B2

公开(公告)日：2019-12-24

申请号：US14948125

申请日：2015-11-20

Applicant: INTEL CORPORATION

Inventor： Penne Y Lee ,  Charlie Wang ,  Ning Ivan Luo

IPC: H04N19/52 ,  H04N19/423

Abstract: Techniques related to reference frame caching for video coding are described herein.

公开(公告)号：US10516876B2

公开(公告)日：2019-12-24

申请号：US15847676

申请日：2017-12-19

Applicant: Intel Corporation

Inventor： Richmond Hicks

IPC: H04N13/271 ,  G03B17/54 ,  G06T7/521 ,  G01B11/25 ,  H04N5/232 ,  G03B21/00 ,  H04N5/235 ,  G06T7/50 ,  H04N13/00

Abstract: Systems, devices, and techniques related to matching features between a dynamic vision sensor and one or both of a dynamic projector or another dynamic vision sensor are discussed. Such techniques include casting a light pattern with projected features having differing temporal characteristics onto a scene and determining the correspondence(s) based on matching changes in detected luminance and temporal characteristics of the projected features.

公开(公告)号：US10511374B2

公开(公告)日：2019-12-17

申请号：US16067806

申请日：2016-06-28

Applicant: INTEL IP CORPORATION

Inventor： Yushu Zhang ,  Yuan Zhu ,  Wenting Chang ,  Gang Xiong ,  Huaning Niu

IPC: H04B7/10 ,  H04B7/06 ,  H04L5/00 ,  H04W88/02 ,  H04W88/08 ,  H04W84/04

Abstract: Described is an apparatus of an Evolved Node-B (eNB) comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to generate a reference signal transmission for an eNB Transmitting (Tx) beam corresponding with at least a first eNB antenna port having a first polarization and a second eNB antenna port having a second polarization. The second circuitry may be operable to process one or more reporting transmissions carrying at least one of a first signal reception indication for a first UE antenna port and a second signal reception indication for a second UE antenna port. The third circuitry may be operable to determine a transmission hypothesis based upon the one or more reporting transmissions.

公开(公告)号：US10483026B2

公开(公告)日：2019-11-19

申请号：US15569978

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Anurag Chaudhry ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/00 ,  H01F10/32 ,  H01L43/10 ,  H01L43/08 ,  H03K19/16 ,  G11C11/16 ,  G11C11/155 ,  H03K19/18 ,  H01F10/26

Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a corresponding spin current; and a stack of metal layers configured to convert the corresponding spin current to a second charge current, wherein the stack of metal layers is coupled to the input magnet.

公开(公告)号：US10468032B2

公开(公告)日：2019-11-05

申请号：US15483246

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Jonathan J. Huang ,  Gokcen Cilingir ,  Tobias Bocklet

IPC: G10L17/00 ,  G10L17/12 ,  G10L17/20 ,  G10L17/04 ,  G10L25/51

Abstract: Techniques related to speaker recognition are discussed. Such techniques include determining context aware confidence values formed of false accept and false reject rates determined by using adaptively updated acoustic environment score distributions matched to current score distributions.

公开(公告)号：US10454495B2

公开(公告)日：2019-10-22

申请号：US14490307

申请日：2014-09-18

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Pranav Kalavade

IPC: G06F9/38 ,  H03M7/02 ,  H03M5/16 ,  G06F3/00

Abstract: Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT.

公开(公告)号：US10451675B2

公开(公告)日：2019-10-22

申请号：US16011356

申请日：2018-06-18

Applicant: Intel Corporation

Inventor： Vinayak Honkote ,  Sriram R. Vangal

IPC: G01R31/3173 ,  G06F1/3206 ,  G06F1/28 ,  G06F1/30 ,  G06F1/3296 ,  G01R31/317 ,  G06F1/26

Abstract: Described is an apparatus which comprises: a state detector which is operable to detect logic states of zero and one in response to a clock edge; and an error detector coupled to the state detector, wherein the error detector is to detect an error in the detected logic states.