公开(公告)号：USD588053S1

公开(公告)日：2009-03-10

申请号：US29306440

申请日：2008-04-09

申请人： Richard Woolley ,  Earl Lucas ,  Dean Carbis ,  Dong Park ,  Michael Boyd

设计人： Richard Woolley ,  Earl Lucas ,  Dean Carbis ,  Dong Park ,  Michael Boyd

公开(公告)号：US20090045450A1

公开(公告)日：2009-02-19

申请号：US11976250

申请日：2007-10-23

申请人： June-mo Koo ,  Suk-pil Kim ,  Young-gu Jin ,  Won-joo Kim ,  In-kyeong Yoo ,  Yoon-dong Park

发明人： June-mo Koo ,  Suk-pil Kim ,  Young-gu Jin ,  Won-joo Kim ,  In-kyeong Yoo ,  Yoon-dong Park

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/66825 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7881

摘要： Provided are a non-volatile memory device, which may have higher integration density, improved or optimal structure, and/or reduce or minimize interference between adjacent cells without using an SOI substrate, and a method of fabricating the non-volatile memory device. The non-volatile memory device may include: a semiconductor substrate comprising a body, and a pair of fins protruding from the body; a buried insulating layer filling between the pair of fins; a pair of floating gate electrodes on outer surfaces of the pair of fins to a height greater than that of the pair of fins; and a control gate electrode on the pair of floating gate electrodes.

摘要翻译： 提供了一种非易失性存储器件，其可以具有更高的集成密度，改进的或最优的结构，和/或减少或最小化相邻单元之间的干扰而不使用SOI衬底，以及制造非易失性存储器件的方法。 非易失性存储器件可以包括：半导体衬底，其包括主体和从主体突出的一对鳍; 埋在绝缘层之间的一对散热片; 一对浮栅电极，其在所述一对翅片的外表面上的高度大于所述一对鳍片的高度; 以及一对浮栅上的控制栅电极。

公开(公告)号：US20080259688A1

公开(公告)日：2008-10-23

申请号：US12010490

申请日：2008-01-25

申请人： Won-joo Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  Suk-pil Kim ,  Jae-woong Hyun ,  Jung-hun Sung ,  Tae-hee Lee

发明人： Won-joo Kim ,  Yoon-dong Park ,  Seung-hoon Lee ,  Suk-pil Kim ,  Jae-woong Hyun ,  Jung-hun Sung ,  Tae-hee Lee

IPC分类号： G11C11/34

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/11568

摘要： A non-volatile memory device includes memory transistors disposed on a semiconductor substrate in a NAND string. A string select transistor is disposed at a first end of the NAND string, and a ground select transistor is disposed at a second end of the NAN string. Bit lines are electrically connected to the semiconductor substrate outside of the string select transistor and a gate electrode of the ground select transistor.

摘要翻译： 非易失性存储器件包括设置在NAND串中的半导体衬底上的存储晶体管。 串选择晶体管设置在NAND串的第一端，并且接地选择晶体管设置在NAN串的第二端。 位线电连接到串选择晶体管外部的半导体衬底和接地选择晶体管的栅电极。

公开(公告)号：US20080242011A1

公开(公告)日：2008-10-02

申请号：US11978567

申请日：2007-10-30

申请人： Seung-hwan Song ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Jae-woong Hyun ,  Choong-ho Lee ,  Tae-hun Kim

发明人： Seung-hwan Song ,  Yoon-dong Park ,  June-mo Koo ,  Suk-pil Kim ,  Jae-woong Hyun ,  Choong-ho Lee ,  Tae-hun Kim

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203

摘要： A method of fabricating a non-volatile memory device according to example embodiments may include forming a semiconductor layer on a substrate. A plurality of lower charge storing layers may be formed on a bottom surface of the semiconductor layer. A plurality of lower control gate electrodes may be formed on the plurality of lower charge storing layers. A plurality of upper charge storing layers may be formed on a top surface of the semiconductor layer. A plurality of upper control gate electrodes may be formed on the plurality of upper charge storing layers, wherein the plurality of lower and upper control gate electrodes may be arranged alternately.

摘要翻译： 根据示例性实施例的制造非易失性存储器件的方法可包括在衬底上形成半导体层。 多个下电荷存储层可以形成在半导体层的底表面上。 可以在多个下电荷存储层上形成多个下控制栅电极。 多个上电荷存储层可以形成在半导体层的顶表面上。 多个上部控制栅极电极可以形成在多个上部电荷存储层上，其中多个下部和上部控制栅电极可以交替布置。

公开(公告)号：US20080212376A1

公开(公告)日：2008-09-04

申请号：US12025372

申请日：2008-02-04

申请人： Yoon-dong Park ,  Jo-won Lee ,  Chung-woo Kim ,  Eun-hong Lee ,  Sun-ae Seo ,  Woo-joo Kim ,  Hee-soon Chae ,  Soo-doo Chae ,  I-hun Song

发明人： Yoon-dong Park ,  Jo-won Lee ,  Chung-woo Kim ,  Eun-hong Lee ,  Sun-ae Seo ,  Woo-joo Kim ,  Hee-soon Chae ,  Soo-doo Chae ,  I-hun Song

IPC分类号： G11C16/06 ,  H01L21/336 ,  G11C7/00

CPC分类号： G11C11/5621 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11551

摘要： Provided are a complementary nonvolatile memory device, methods of operating and manufacturing the same, a logic device and semiconductor device having the same, and a reading circuit for the same. The complementary nonvolatile memory device includes a first nonvolatile memory and a second nonvolatile memory which are sequentially stacked and have a complementary relationship. The first and second nonvolatile memories are arranged so that upper surfaces thereof are contiguous.

摘要翻译： 提供了一种互补的非易失性存储器件，其操作和制造方法，逻辑器件和具有该非易失性存储器件的半导体器件及其读取电路。 互补非易失性存储器件包括顺序堆叠并具有互补关系的第一非易失性存储器和第二非易失性存储器。 第一和第二非易失性存储器被布置成使得其上表面相邻。

公开(公告)号：US20080202488A1

公开(公告)日：2008-08-28

申请号：US11910611

申请日：2006-04-19

申请人： Soo-Kwang Kim ,  Hee-Dong Park ,  Joon-Ho Chang ,  Jong-Ho Kim

发明人： Soo-Kwang Kim ,  Hee-Dong Park ,  Joon-Ho Chang ,  Jong-Ho Kim

IPC分类号： B28D1/04

CPC分类号： B28D1/121 ,  B24D5/123 ,  B24D99/005 ,  B27B33/02

摘要： The invention provides a cutting segment for a cutting tool for cutting or drilling a brittle work piece such as stone, bricks, concrete and asphalt, and a cutting tool having the cutting segment. The cutting segment includes a cutting surface for cutting a work piece and a plurality of abrasive particle layers. The abrasive particle layers are disposed perpendicular to a cutting direction. Each of the abrasive layers has a plurality of abrasive particle rows in a width direction of the cutting segment. Each of the abrasive rows has a plurality of abrasive particles arranged in a line. Further, the abrasive layers have a plurality of blank sections therebetween. In the blanks sections, abrasive particles are absent or have a concentration of 70% or less with respect to those in the abrasive rows. In addition, the blank sections include relatively thick blank sections and relatively thin blank sections.

摘要翻译： 本发明提供了一种用于切割或钻削诸如石头，砖，混凝土和沥青的脆性工件的切割工具的切割部分和具有切割部分的切割工具。 切割段包括用于切割工件和多个磨料颗粒层的切割表面。 研磨颗粒层垂直于切割方向设置。 每个研磨层在切割段的宽度方向上具有多个研磨颗粒行。 每个磨料列具有排列成一行的多个磨料颗粒。 此外，磨料层之间具有多个坯料部分。 在坯料部分中，磨料颗粒不存在或者相对于磨料行的浓度为70％以下。 另外，空白部分包括相对较厚的空白部分和相对较薄的空白部分。

公开(公告)号：US20080017934A1

公开(公告)日：2008-01-24

申请号：US11723074

申请日：2007-03-16

申请人： Suk-Pil Kim ,  Yoon-Dong Park ,  Won-Joo Kim

发明人： Suk-Pil Kim ,  Yoon-Dong Park ,  Won-Joo Kim

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/0657 ,  H01L29/42392 ,  H01L29/78696

摘要： Provided are relatively higher-performance wire-type semiconductor devices and relatively economical methods of fabricating the same. A wire-type semiconductor device may include at least one pair of support pillars protruding above a semiconductor substrate, at least one fin protruding above the semiconductor substrate and having ends connected to the at least one pair of support pillars, at least one semiconductor wire having ends connected to the at least one pair of support pillars and being separated from the at least one fin, a common gate electrode surrounding the surface of the at least one semiconductor wire, and a gate insulating layer between the at least one semiconductor wire and the common gate electrode.

摘要翻译： 提供了相对较高性能的线型半导体器件和相对经济的制造方法。 线型半导体器件可以包括突出在半导体衬底上方的至少一对支撑柱，至少一个突出于半导体衬底之上并具有连接到至少一对支撑柱的端子的鳍片，至少一个半导体线材具有 连接到所述至少一对支撑柱并且与所述至少一个鳍分离的端部，围绕所述至少一个半导体线的表面的公共栅电极以及所述至少一个半导体线和所述至少一个半导体线之间的栅极绝缘层 共栅电极。

公开(公告)号：US20070284648A1

公开(公告)日：2007-12-13

申请号：US11723222

申请日：2007-03-19

申请人： Yoon-Dong Park ,  Won-Joo Kim ,  June-Mo Koo ,  Suk-Pil Kim ,  Jae-Woong Hyun ,  Jung-Hoon Lee

发明人： Yoon-Dong Park ,  Won-Joo Kim ,  June-Mo Koo ,  Suk-Pil Kim ,  Jae-Woong Hyun ,  Jung-Hoon Lee

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L21/764 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792

摘要： The non-volatile memory device may include a semiconductor substrate having a body and a pair of fins. A bridge insulating layer may non-electrically connect upper portions of the pair of fins to define a void between the pair of fins. Outer surfaces of the pair of fins are the surfaces of the pair of fins that do not face the void and inner surfaces of the pair of fins are the surfaces of the pair of fins that do face the void. The non-volatile memory device may further include at least one control gate electrode that may cover at least a portion of outer surfaces of the pair of fins, may extend over the bridge insulating layer, and may be isolated from the semiconductor substrate. At least one pair of gate insulating layers may be between the at least one control gate electrode and the pair of fins, and at least one pair of storage nodes may be between the at least one pair of gate insulating layers and the at least one control gate electrode.

摘要翻译： 非易失性存储器件可以包括具有主体和一对翅片的半导体衬底。 桥式绝缘层可以非电连接该对翅片的上部，以限定一对翅片之间的空隙。 一对翅片的外表面是一对翅片的不面向空隙的表面，并且一对翅片的内表面是面对空隙的一对翅片的表面。 非易失性存储器件还可以包括至少一个可覆盖该对散热片的外表面的至少一部分的控制栅极电极，可以在该桥绝缘层上延伸，并且可以与该半导体衬底隔离。 至少一对栅极绝缘层可以在至少一个控制栅极电极和一对散热片之间，并且至少一对存储节点可以位于至少一对栅极绝缘层之间，并且至少一个控制 栅电极。

公开(公告)号：US20070247913A1

公开(公告)日：2007-10-25

申请号：US11812574

申请日：2007-06-20

申请人： Yoon-dong Park ,  Sun-ae Seo ,  Choong-rae Cho ,  Won-joo Kim ,  Sang-min Shin

发明人： Yoon-dong Park ,  Sun-ae Seo ,  Choong-rae Cho ,  Won-joo Kim ,  Sang-min Shin

IPC分类号： G11C11/02 ,  H01L21/8244 ,  H01L27/11

CPC分类号： H01L29/7926 ,  H01L29/42332 ,  H01L29/7887 ,  H01L29/7923

摘要： Disclosed are a multi-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the multi-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of channels disposed perpendicularly to the upper surface of the semiconductor substrate; a plurality of storage nodes disposed on opposite sides of the channels perpendicularly the upper surface of the semiconductor substrate; a control gate surrounding upper portions of the channels and the storage nodes, and side surfaces of the storage nodes; and an insulating film formed between the channels and the storage nodes, between the channels and the control gate, and between the storage nodes and the control gate.

摘要翻译： 公开了一种多位非易失性存储器件，其操作方法以及制造该多位非易失性存储器件的方法。 多位非易失性存储器件的单元可以形成在半导体衬底上，可以包括：垂直于半导体衬底的上表面设置的多个通道; 多个存储节点，其设置在所述通道的相对侧，垂直于所述半导体衬底的上表面; 围绕通道和存储节点的上部以及存储节点的侧表面的控制门; 以及形成在通道和存储节点之间，通道和控制栅极之间以及存储节点和控制门之间的绝缘膜。

公开(公告)号：US07256447B2

公开(公告)日：2007-08-14

申请号：US11181724

申请日：2005-07-15

申请人： Yoon-dong Park ,  Sun-ae Seo ,  Choong-rae Cho ,  Won-joo Kim ,  Sang-min Shin

发明人： Yoon-dong Park ,  Sun-ae Seo ,  Choong-rae Cho ,  Won-joo Kim ,  Sang-min Shin

IPC分类号： H01L29/788

CPC分类号： H01L29/7926 ,  H01L29/42332 ,  H01L29/7887 ,  H01L29/7923

摘要： Disclosed are a muli-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the muli-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of channels disposed perpendicularly to the upper surface of the semiconductor substrate; a plurality of storage nodes disposed on opposite sides of the channels perpendicularly the upper surface of the semiconductor substrate; a control gate surrounding upper portions of the channels and the storage nodes, and side surfaces of the storage nodes; and an insulating film formed between the channels and the storage nodes, between the channels and the control gate, and between the storage nodes and the control gate.

摘要翻译： 公开了多位非易失性存储器件，其操作方法以及制造多位非易失性存储器件的方法。 多晶硅非易失性存储器件的单元可以形成在半导体衬底上，可以包括：垂直于半导体衬底的上表面设置的多个沟道; 多个存储节点，其设置在所述通道的相对侧，垂直于所述半导体衬底的上表面; 围绕通道和存储节点的上部以及存储节点的侧表面的控制门; 以及形成在通道和存储节点之间，通道和控制栅极之间以及存储节点和控制门之间的绝缘膜。