公开(公告)号：US20110298018A1

公开(公告)日：2011-12-08

申请号：US12937502

申请日：2010-06-28

Applicant: Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

Inventor： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/4983 ,  H01L21/28105 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: The invention provides a transistor, including: a substrate having a channel region; a source region and a drain region on two ends of the channel region of the substrate respectively; a gate high-K dielectric layer on a top surface of the substrate above the channel region between the source region and the drain region; an interfacial layer under the gate high-K dielectric layer, including a first portion near the source region and a second portion near the drain region, wherein an equivalent oxide thickness of the first portion is larger than that of the second portion. An asymmetric replacement metal gate forms an asymmetric interfacial layer, which is thin at the drain region side and thick at the source region side. At the thin drain region side, the short channel effect is significant and the asymmetric interfacial layer advantageously suppresses the short channel effect. At the thick source region side, the carrier mobility has a large influence on the device, and the asymmetric interfacial layer prevents the carrier mobility from decreasing. Further, the asymmetric replacement metal gate implements an asymmetric metal work function.

Abstract translation: 本发明提供一种晶体管，包括：具有沟道区的衬底; 分别在所述衬底的沟道区域的两端上的源极区域和漏极区域; 位于源极区域和漏极区域之间的沟道区域上方的衬底顶表面上的栅极高K电介质层; 在栅极高K电介质层下面的界面层，包括靠近源区的第一部分和靠近漏极区的第二部分，其中第一部分的等效氧化物厚度大于第二部分的等效氧化物厚度。 不对称替代金属栅极形成不对称界面层，其在漏极区侧较薄，在源极区侧较厚。 在薄漏极侧，短沟道效应显着，不对称界面层有利地抑制了短沟道效应。 在较厚的源极侧，载流子迁移率对器件的影响较大，不对称界面层阻止载流子迁移率降低。 此外，不对称替代金属栅极实现了非对称金属功能。

公开(公告)号：US20110291184A1

公开(公告)日：2011-12-01

申请号：US13062911

申请日：2010-09-26

Applicant: Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

Inventor： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

IPC: H01L29/78 ,  H01L21/336 ,  B82Y99/00

CPC classification number: H01L29/78687 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66772

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate; an epitaxial semiconductor layer formed on two side portions of the semiconductor substrate; a gate stack formed at a central position on the semiconductor substrate and abutting the epitaxial semiconductor layer, the gate comprising a gate conductor layer and a gate dielectric layer which is sandwiched between the gate conductor layer and the semiconductor substrate and surrounding the lateral surfaces of the gate conductor layer; and a sidewall spacer formed on the epitaxial semiconductor layer and surrounding the gate. The method for manufacturing the above semiconductor structure comprises forming raised source/drain regions in the epitaxial semiconductor layer utilizing the sacrificial gate. The semiconductor structure and the method for manufacturing the same can simplify the fabrication process for an ultra-thin SOI transistor and reduce the ON-state resistance and power consumption of the transistor.

Abstract translation: 本申请公开了一种半导体结构及其制造方法。 半导体结构包括半导体衬底; 形成在所述半导体衬底的两个侧面上的外延半导体层; 形成在所述半导体衬底上的中心位置并与所述外延半导体层邻接的栅极叠层，所述栅极包括栅极导体层和栅极电介质层，所述栅极介电层夹在所述栅极导体层和所述半导体衬底之间， 栅极导体层; 以及形成在外延半导体层上并围绕栅极的侧壁间隔物。 制造上述半导体结构的方法包括利用牺牲栅极在外延半导体层中形成凸起的源/漏区。 半导体结构及其制造方法可以简化超薄SOI晶体管的制造工艺，并降低晶体管的导通电阻和功耗。

公开(公告)号：US08053838B2

公开(公告)日：2011-11-08

申请号：US12146728

申请日：2008-06-26

Applicant: Xiaomeng Chen ,  Byeong Yeol Kim ,  Mahender Kumar ,  Huilong Zhu

Inventor： Xiaomeng Chen ,  Byeong Yeol Kim ,  Mahender Kumar ,  Huilong Zhu

IPC: H01L29/00 ,  H01L21/20

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure, a fabrication method, and a design structure for a FinFet. The FinFet includes a dielectric layer, a central semiconductor fin region on the dielectric layer, a first semiconductor seed region on the dielectric layer, and a first strain creating fin region. The first semiconductor seed region is sandwiched between the first strain creating fin region and the dielectric layer. The first semiconductor seed region includes a first semiconductor material. The first strain creating fin region includes the first semiconductor material and a second semiconductor material different than the first semiconductor material. A first atom percent of the first semiconductor material in the first semiconductor seed region is different than a second atom percent of the first semiconductor material in the first strain creating fin region.

Abstract translation: FinFet的半导体结构，制造方法和设计结构。 FinFet包括电介质层，电介质层上的中央半导体鳍片区域，电介质层上的第一半导体种子区域和第一应变产生鳍片区域。 第一半导体种子区域夹在第一应变产生鳍区域和电介质层之间。 第一半导体种子区域包括第一半导体材料。 第一应变产生鳍区域包括第一半导体材料和与第一半导体材料不同的第二半导体材料。 第一半导体晶种区域中的第一半导体材料的第一原子百分比不同于第一应变产生鳍区域中的第一半导体材料的第二原子百分比。

公开(公告)号：US20110266677A1

公开(公告)日：2011-11-03

申请号：US12990990

申请日：2010-09-19

Applicant: Huilong Zhu ,  Haizhou Yin ,  Zhijong Luo

Inventor： Huilong Zhu ,  Haizhou Yin ,  Zhijong Luo

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/522 ,  H01L21/32051 ,  H01L21/76823 ,  H01L21/76838 ,  H01L21/76873 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor structure and a manufacturing method thereof. The method comprises; providing a semiconductor substrate comprising semiconductor devices; depositing a copper diffusion barrier layer on the semiconductor substrate; forming a copper composite layer on the copper diffusion barrier layer; decomposing the copper composite at corresponding positions, where copper interconnection is to be formed, into copper according to the shape of the copper interconnection; and etching off the undecomposed copper composite and the copper diffusion barrier layer underneath, to interconnect the semiconductor devices. The present invention is adaptive for manufacturing interconnection in integrated circuits.

Abstract translation: 本发明提供一种半导体结构及其制造方法。 该方法包括： 提供包括半导体器件的半导体衬底; 在所述半导体衬底上沉积铜扩散阻挡层; 在铜扩散阻挡层上形成铜复合层; 根据铜互连的形状，将要形成铜互连的相应位置处的铜复合物分解成铜; 并且在下面蚀刻未分解的铜复合物和铜扩散阻挡层，以使半导体器件互连。 本发明适用于制造集成电路中的互连。

公开(公告)号：US20110260258A1

公开(公告)日：2011-10-27

申请号：US13063731

申请日：2010-06-22

Applicant: Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

Inventor： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/7845

Abstract: The devices are manufactured by replacement gate process and replacement sidewall spacer process, and both tensile stress in the channel region of NMOS device and compressive stress in the channel region of PMOS device are increased by forming a first stress layer with compressive stress in the space within the first metal gate layer of NMOS and a second stress layer with tensile stress in the space within the second metal gate layer of PMOS, respectively. After formation of the stress layers, sidewall spacers of the gate stacks of PMOS and NMOS devices are removed so as to release stress in the channel regions. In particular, stress structure with opposite stress may be formed on sidewalls of the gate stacks of the NMOS device and PMOS device and on a portion of the source region and the drain region, in order to further increase both tensile stress of the NMOS device and compressive stress of the PMOS device.

Abstract translation: 器件通过更换栅极工艺和替换侧壁间隔工艺制造，NMOS器件的沟道区域中的拉伸应力和PMOS器件的沟道区域中的压应力均增加，在第一应力层内形成压缩应力 NMOS的第一金属栅极层和在PMOS的第二金属栅极层内的空间中具有拉伸应力的第二应力层。 在形成应力层之后，去除PMOS和NMOS器件的栅叠层的侧壁间隔物，以释放沟道区中的应力。 特别地，具有相反应力的应力结构可以形成在NMOS器件和PMOS器件的栅极堆叠的侧壁上，并且在源极区域和漏极区域的一部分上形成，以便进一步增加NMOS器件的拉伸应力和 PMOS器件的压应力。

公开(公告)号：US20110193166A1

公开(公告)日：2011-08-11

申请号：US12700797

申请日：2010-02-05

Applicant: Qingqing LIANG ,  Huilong ZHU ,  Zhijiong LUO ,  Haizhou YIN

Inventor： Qingqing LIANG ,  Huilong ZHU ,  Zhijiong LUO ,  Haizhou YIN

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L27/1203 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L29/6675 ,  H01L29/78615 ,  H01L29/78624 ,  H01L29/78687

Abstract: The present invention generally relates to a semiconductor structure and method, and more specifically, to a structure and method for reducing floating body effect of silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). An integrated circuit (IC) structure includes an SOI substrate and at least one MOSFET formed on the SOI substrate. Additionally, the IC structure includes an asymmetrical source-drain junction in the at least one MOSFET by damaging a pn junction to reduce floating body effects of the at least one MOSFET.

Abstract translation: 本发明一般涉及半导体结构和方法，更具体地说，涉及用于减少绝缘体上硅（SOI）金属氧化物半导体场效应晶体管（MOSFET）的浮体效应的结构和方法。 集成电路（IC）结构包括SOI衬底和形成在SOI衬底上的至少一个MOSFET。 此外，IC结构包括通过损坏pn结在至少一个MOSFET中的不对称源极 - 漏极结，以减少至少一个MOSFET的浮体效应。

公开(公告)号：US20110169088A1

公开(公告)日：2011-07-14

申请号：US12686402

申请日：2010-01-13

Applicant: Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin

Inventor： Huilong Zhu ,  Zhijiong Luo ,  Qingqing Liang ,  Haizhou Yin

IPC: H01L27/12 ,  H01L21/762

CPC classification number: H01L27/1207 ,  H01L21/76251 ,  H01L21/8221 ,  H01L27/0688 ,  H01L29/66545

Abstract: A device and method is provided that in one embodiment provides a first semiconductor device including a first gate structure on a first channel region, in which a first source region and a first drain region are present on opposing sides of the first channel region, in which a metal nitride spacer is present on only one side of the first channel region. The device further includes a second semiconductor device including a second gate structure on a second channel region, in which a second source region and a second drain region are present on opposing sides of the second channel region. Interconnects may be present providing electrical communication between the first semiconductor device and the second semiconductor device, in which at least one of the first semiconductor device and the second semiconductor device is inverted. A structure having a reverse halo dopant profile is also provided.

Abstract translation: 提供了一种装置和方法，在一个实施例中提供了第一半导体器件，其包括在第一沟道区上的第一栅极结构，其中第一源区和第一漏区存在于第一沟道区的相对侧上，其中 金属氮化物间隔物仅存在于第一沟道区的一侧。 该器件还包括在第二沟道区上包括第二栅极结构的第二半导体器件，其中第二源区和第二漏区存在于第二沟道区的相对侧上。 可以存在互连件，其提供第一半导体器件和第二半导体器件之间的电连通，其中第一半导体器件和第二半导体器件中的至少一个被反转。 还提供了具有反向卤素掺杂剂分布的结构。

公开(公告)号：US07977712B2

公开(公告)日：2011-07-12

申请号：US12059059

申请日：2008-03-31

Applicant: Huilong Zhu ,  Hong Lin ,  Katherine L. Saenger ,  Kai Xiu ,  Haizhou Yin

Inventor： Huilong Zhu ,  Hong Lin ,  Katherine L. Saenger ,  Kai Xiu ,  Haizhou Yin

IPC: H01L29/04

CPC classification number: H01L21/823807 ,  H01L21/28132 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau region contiguous with and adjoining a sloped incline region. Within the context of a CMOS semiconductor structure, such a semiconductor substrate allows for fabrication of a pFET and an nFET upon different crystallographic orientation semiconductor regions, while one of the pFET and the nFET (i.e., typically the pFET) has asymmetric source and drain regions.

Abstract translation: 诸如CMOS半导体结构的半导体结构包括具有不对称的多个源区和漏区的场效应器件。 通过使用包括与倾斜斜面区域相邻并相邻的水平平台区域的半导体衬底制造半导体结构来诱导这种源区和漏区不对称。 在CMOS半导体结构的上下文中，这种半导体衬底允许在不同的晶体取向半导体区域上制造pFET和nFET，而pFET和nFET（即，通常为pFET）中的一个具有不对称的源极和漏极区域 。

公开(公告)号：US07977178B2

公开(公告)日：2011-07-12

申请号：US12395904

申请日：2009-03-02

Applicant: Seong-Dong Kim ,  Zhijiong Lou ,  Huilong Zhu

Inventor： Seong-Dong Kim ,  Zhijiong Lou ,  Huilong Zhu

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7848

Abstract: A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap.

Abstract translation: 半导体器件包括形成在本体衬底上的掩埋绝缘体层; 形成在所述掩埋绝缘体层上并对应于场效应晶体管（FET）的体区的第一类型半导体材料; 形成在所述掩埋绝缘体层上，邻近所述本体区域的相对侧并且对应于所述FET的源极和漏极区域的第二类型的半导体材料; 所述第二类型的半导体材料具有与所述第一类型的半导体材料不同的带隙; 其中FET的源极p / n结基本上位于具有较低带隙的第一和第二类型的半导体材料中的任何一个中，并且FET的漏极侧p / n结基本上完全位于 第一和第二类型的具有较高带隙的半导体材料。

公开(公告)号：US20110163359A1

公开(公告)日：2011-07-07

申请号：US13047037

申请日：2011-03-14

Applicant: Huilong Zhu

Inventor： Huilong Zhu

IPC: H01L29/78

CPC classification number: H01L21/3083 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/30608 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823437

Abstract: An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation of Ge, B, Ga, In, As, P, Sb, or inert atoms is performed parallel to each of the two facets joined by the ridge causing damage to implanted portions of the masking material layer, which are removed selective to undamaged portions of the masking material layer along the ridge and having a constant width. The semiconductor layer and a dielectric oxide layer underneath are etched selective to the remaining portions of the dielectric nitride. Employing remaining portions of the dielectric oxide layer as an etch mask, the gate conductor layer is patterned to form gate conductor lines having a constant width.

Abstract translation: 半导体层的各向异性湿蚀刻产生由沿着半导体层上的电介质硬掩模层中的图案的中心延伸的脊接合的刻面。 去除介电硬掩模层并沉积保形掩模材料层。 与由脊组合的两个小平面中的每一个平行地进行Ge，B，Ga，In，As，P，Sb或惰性原子的角度离子注入，从而对掩蔽材料层的注入部分造成损害， 屏蔽材料层沿着脊的未损坏部分并且具有恒定的宽度。 在其下面的半导体层和电介质氧化物层对电介质氮化物的其余部分进行蚀刻选择性。 使用电介质氧化物层的剩余部分作为蚀刻掩模，对栅极导体层进行构图以形成具有恒定宽度的栅极导体线。