公开(公告)号：US20070252237A1

公开(公告)日：2007-11-01

申请号：US11411341

申请日：2006-04-26

申请人： Young-Gun Ko ,  Ja-Hum Ku ,  Minchul Sun ,  Robert Weiser

发明人： Young-Gun Ko ,  Ja-Hum Ku ,  Minchul Sun ,  Robert Weiser

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Electrically programmable integrated fuses are provided for low power applications. Integrated fuse devices have stacked structures with a polysilicon layer and a conductive layer formed on the polysilicon layer. The integrated fuses have structural features that enable the fuses to be reliably and efficiently programmed using low programming currents/voltages, while achieving consistency in fusing locations. For example, programming reliability and consistency is achieved by forming the conductive layers with varied thickness and forming the polysilicon layers with varied doping profiles, to provide more precise localized regions in which fusing events readily occur.

摘要翻译： 为低功率应用提供电可编程集成保险丝。 集成保险丝装置具有多晶硅层和形成在多晶硅层上的导电层的堆叠结构。 集成保险丝具有结构特征，可以使熔断器在低编程电流/电压下可靠且高效地编程，同时实现熔断位置的一致性。 例如，通过形成具有不同厚度的导电层并且形成具有变化的掺杂分布的多晶硅层来实现编程可靠性和一致性，以提供更精确的局部区域，其中容易发生熔融事件。

公开(公告)号：US20060270205A1

公开(公告)日：2006-11-30

申请号：US11498197

申请日：2006-08-03

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim

IPC分类号： H01L21/4763 ,  H01L23/52

CPC分类号： H01L21/823437 ,  H01L21/28247 ,  H01L29/4941 ,  H01L29/6656

摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).

公开(公告)号：US20060231906A1

公开(公告)日：2006-10-19

申请号：US11254081

申请日：2005-10-19

申请人： Young-gun Ko ,  Ja-hum Ku

发明人： Young-gun Ko ,  Ja-hum Ku

IPC分类号： H01L29/76

CPC分类号： H01L22/12

摘要： Provided are an improved structure for measuring gate misalignment and a measuring method thereof. The structure includes an active region and a device isolation region, a first gate group including a plurality of gates extending in one direction at one side of the active region, widths of the gates being the same with one another and lengths of the respective gates overlapping with the active region being different from one another, and a second gate group including a plurality of gates extending in one direction at the other side of the active region, widths of the gates being the same as one another and lengths of the respective gates overlapping with the active region being different from one another.

摘要翻译： 提供了用于测量栅极未对准的改进的结构及其测量方法。 该结构包括有源区和器件隔离区，第一栅极组包括在有源区的一侧沿一个方向延伸的多个栅极，栅极的宽度彼此相同，各栅极的长度重叠 其中所述有源区彼此不同;以及第二栅极组，包括在所述有源区的另一侧沿一个方向延伸的多个栅极，所述栅极的宽度彼此相同，并且各个栅极的长度重叠 活性区域彼此不同。

公开(公告)号：US20060223296A1

公开(公告)日：2006-10-05

申请号：US11180885

申请日：2005-07-13

申请人： Min-Chul Sun ,  Ja-Hum Ku ,  Sug-Woo Jung ,  Sung-Kee Han ,  Min-Joo Kim ,  Kwan-Jong Roh

发明人： Min-Chul Sun ,  Ja-Hum Ku ,  Sug-Woo Jung ,  Sung-Kee Han ,  Min-Joo Kim ,  Kwan-Jong Roh

IPC分类号： H01L21/3205 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/28518 ,  H01L29/665

摘要： A semiconductor device having a self-aligned silicide layer and a method thereof are provided. The device includes a device isolation layer formed on the substrate to define an active region and a gate pattern crossing over the active region. A spacer insulating layer is formed on both sidewalls of the gate pattern. First and second salicide layers are formed on an upper portion of the gate pattern, and the first salicide layer is formed on the active region between the spacer insulating layer and the device isolation layer. The first and the second salicide layers on the gate pattern are alternately formed to be connected with each other. The first salicide layer is agglomeratedly formed on a narrow gate pattern, and the second salicide layer is formed within interrupted portions of the first salicide layer, thereby forming a patched salicide layer.

摘要翻译： 提供了具有自对准硅化物层的半导体器件及其方法。 该器件包括在衬底上形成的器件隔离层，以限定有源区和跨越有源区的栅极图案。 在栅极图案的两个侧壁上形成间隔绝缘层。 第一和第二自对准硅化物层形成在栅极图案的上部，并且第一自对准硅化物层形成在间隔绝缘层和器件隔离层之间的有源区上。 栅极图案上的第一和第二自对准硅化物层交替地形成为彼此连接。 第一自对准硅化物层在窄栅极图案上聚集形成，并且第二自对准硅化物层形成在第一自对准硅化物层的中断部分内，从而形成修补的自对准硅化物层。

公开(公告)号：US07098123B2

公开(公告)日：2006-08-29

申请号：US10780244

申请日：2004-02-17

申请人： Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

发明人： Seong-Jun Heo ,  Sun-Pil Youn ,  Sung-Man Kim ,  Si-Young Choi ,  Gil-Heyun Choi ,  Ja-Hum Ku ,  Chang-Won Lee ,  Jong-Myeong Lee ,  Kwon-Sun Ryu

IPC分类号： H01L21/28

CPC分类号： H01L21/28061 ,  H01L21/28088 ,  H01L29/4941 ,  H01L29/4966 ,  H01L29/6659 ,  H01L29/7833

摘要： Methods of forming a semiconductor device having a metal gate electrode include sequentially forming a gate insulator, a gate polysilicon layer and a metal-gate layer on a semiconductor substrate. The metal-gate layer and the gate polysilicon layer are sequentially patterned to form a gate pattern comprising a stacked gate polysilicon pattern and a metal-gate pattern. An oxidation barrier layer is formed to cover at least a portion of a sidewall of the metal-gate pattern.

摘要翻译： 形成具有金属栅电极的半导体器件的方法包括在半导体衬底上顺序地形成栅极绝缘体，栅极多晶硅层和金属栅极层。 金属栅极层和栅极多晶硅层被顺序地图案化以形成包括堆叠栅极多晶硅图案和金属栅极图案的栅极图案。 形成氧化阻挡层以覆盖金属 - 栅极图案的侧壁的至少一部分。

公开(公告)号：US07005367B2

公开(公告)日：2006-02-28

申请号：US10612041

申请日：2003-07-03

申请人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Min-Chul Sun ,  Sun-Pil Youn

发明人： Ja-Hum Ku ,  Chang-Won Lee ,  Seong-Jun Heo ,  Min-Chul Sun ,  Sun-Pil Youn

IPC分类号： H01L21/441

CPC分类号： H01L27/11521 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/31612 ,  H01L27/115

摘要： A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit a silicon oxide layer on a semiconductor substrate, which may include a conductive material layer. A silicon nitride layer may then be formed on the silicon oxide layer by performing a general CVD process. Next, the silicon nitride layer may be etched until the silicon oxide layer is exposed. Because of the difference in etching selectivity between silicon nitride and silicon oxide, portions of the silicon nitride layer may remain on sidewalls of the conductive material layer. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls.

摘要翻译： 提供一种制造包括双间隔件的半导体器件的方法。 可以通过供应氮源气体在反应室中产生和保持氮气氛。 然后可以将硅源气体和氧源气体供应到反应室以在可包括导电材料层的半导体衬底上沉积氧化硅层。 然后可以通过执行一般CVD工艺在氧化硅层上形成氮化硅层。 接下来，可以蚀刻氮化硅层直到氧化硅层露出。 由于氮化硅和氧化硅之间的蚀刻选择性的差异，氮化硅层的部分可能残留在导电材料层的侧壁上。 结果，可以在侧壁上形成由氧化硅层和氮化硅层形成的双重间隔物。

公开(公告)号：US20050196960A1

公开(公告)日：2005-09-08

申请号：US11113980

申请日：2005-04-26

申请人： Kyeong-Mo Koo ,  Ja-Hum Ku ,  Hye-Jeong Park

发明人： Kyeong-Mo Koo ,  Ja-Hum Ku ,  Hye-Jeong Park

IPC分类号： C23C14/02 ,  C23C14/16 ,  C23C14/58 ,  H01L21/28 ,  H01L21/336 ,  H01L21/4763

CPC分类号： C23C14/5806 ,  C23C14/021 ,  C23C14/165 ,  C23C14/5873 ,  H01L21/28052 ,  H01L29/665

摘要： A metal-containing film is formed on a silicon-containing conductive region at a temperature where the metal of the metal-containing film and silicon of the semiconductor substrate react with each other to form a diffusion restraint interface film interposed between the metal-containing film and silicon of the and the semiconductor substrate. The resultant structure is annealed so that metal of the metal-containing film and silicon of the silicon-containing conductive region react with each other to form a metal silicide film.

摘要翻译： 在含金属的膜的金属和半导体基板的硅彼此反应的温度下，在含硅导电区域上形成含金属的膜，以形成介于含金属膜的扩散抑制界面膜 和半导体衬底的硅。 将所得结构退火，使含金属的膜的金属和含硅导电区域的硅彼此反应，形成金属硅化物膜。

公开(公告)号：US20050158996A1

公开(公告)日：2005-07-21

申请号：US10988848

申请日：2004-11-16

申请人： Min-Joo Kim ,  Ja-Hum Ku ,  Min-Chul Sun ,  Kwan-Jong Roh

发明人： Min-Joo Kim ,  Ja-Hum Ku ,  Min-Chul Sun ,  Kwan-Jong Roh

IPC分类号： H01L21/24 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/78 ,  H01L21/322

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518

摘要： A nickel salicide process includes preparing a substrate having a silicon region and an insulating region containing silicon. Nickel is deposited on the substrate, and the nickel is annealed at a first temperature of 300° C. to 380° C. to selectively form a mono-nickel mono-silicide layer on the silicon region and to leave an unreacted nickel layer on the insulating region. The unreacted nickel layer is selectively removed to expose the insulating region and to leave the mono-nickel mono-silicide layer on the silicon region. Subsequently, the mono-nickel mono-silicide layer is annealed at a second temperature which is higher than the first temperature to form a thermally stable mono-nickel mono-silicide layer and without a phase transition of the mono-nickel mono-silicide layer.

摘要翻译： 镍硅化物工艺包括制备具有硅区和含硅绝缘区的衬底。 镍沉积在衬底上，并且镍在300℃至380℃的第一温度下退火，以在硅区域上选择性地形成单镍单硅化物层，并在其上留下未反应的镍层 绝缘区域。 选择性地去除未反应的镍层以暴露绝缘区域并且在硅区域上留下单镍单硅化物层。 随后，在高于第一温度的第二温度下对单镍单硅化物层进行退火，以形成热稳定的单镍一硅化物层，并且不存在单镍一硅化物层的相变。