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133 条记录 (耗时 0.017 秒)

    Power supply structure
    73.
    发明授权
    Power supply structure 失效
    电源结构

    公开(公告)号：US06724639B2

    公开(公告)日：2004-04-20

    申请号：US10198376

    申请日：2002-07-18

    申请人： Sheng-Nan Tsai ,  Chen-Chiang Su ,  Jia-Li Tsai

    发明人： Sheng-Nan Tsai ,  Chen-Chiang Su ,  Jia-Li Tsai

    IPC分类号： H01R1216

    CPC分类号： H05K5/0069 ,  H05K7/142

    摘要： A power supply structure includes a first circuit board, a second circuit board, a first connecting part and a second connecting part. The second circuit board is horizontally disposed above the first circuit board, a first connecting part electrically connected between the first circuit board and the second circuit board for transmitting signals of the first circuit board and second circuit and a second connecting part electrically connected between the first circuit board and the second circuit board for conducting currents of the first circuit board and the second circuit.

    摘要翻译： 电源结构包括第一电路板，第二电路板，第一连接部和第二连接部。 第二电路板水平地设置在第一电路板的上方，电连接在第一电路板和第二电路板之间用于传输第一电路板和第二电路的信号的第一连接部分和电连接在第一电路板和第二电路板之间的第二连接部分 电路板和用于传导第一电路板和第二电路的电流的第二电路板。

    Junction formation with diffusion barrier for silicide contacts and method for forming
    74.
    发明授权
    Junction formation with diffusion barrier for silicide contacts and method for forming 失效
    用于硅化物接触的扩散阻挡层的连接形成和形成方法

    公开(公告)号：US06444553B1

    公开(公告)日：2002-09-03

    申请号：US09110377

    申请日：1997-09-15

    申请人： Wanda Zagozdson-Wosik ,  Jia Li

    发明人： Wanda Zagozdson-Wosik ,  Jia Li

    IPC分类号： H01L2128

    CPC分类号： H01L21/28518 ,  H01L21/2251

    摘要： Method and apparatus are provided for a semiconductor device including a junction and contact having a diffusion barrier to control silicidation of a silicon substrate. A dopant is applied in excess of an amount required to form a junction and the dopant chemically reacts with a metal to form a compound which serves as a barrier layer to prevent silidication in the substrate.

    摘要翻译： 提供了一种半导体器件的方法和装置，该半导体器件包括具有扩散势垒的接点和接触件，以控制硅衬底的硅化。 施加掺杂剂超过形成结的所需量，并且掺杂剂与金属发生化学反应以形成用作阻挡层的化合物，以防止在衬底中的硅化。

    Nitride encapsulated thin film transistor fabrication technique
    77.
    发明授权
    Nitride encapsulated thin film transistor fabrication technique 失效
    氮化物封装薄膜晶体管制造技术

    公开(公告)号：US5616933A

    公开(公告)日：1997-04-01

    申请号：US543404

    申请日：1995-10-16

    申请人： Jia Li

    发明人： Jia Li

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L23/29 ,  H01L29/786 ,  H01L29/04 ,  H01L23/58

    CPC分类号： H01L29/66765 ,  H01L23/291 ,  H01L29/78678 ,  H01L2924/0002

    摘要： A thin film transistor includes a thin film transistor body above a gate electrode. The thin film transistor body is hydrogenated to prevent the transistor body from apparently capturing and releasing electrons. The transistor body itself is coated with an upper and lower layer of silicon nitride to prevent the trapped hydrogen from migrating out of the transistor body over time. This is formed by depositing a layer of silicon dioxide, then a layer of silicon nitride over the gate electrode, followed by deposition of a polysilicon layer which is then etched to form the transistor body. This is hydrogenated after threshold adjustment implant and source/drain implant and subsequently coated with an upper sealing layer of silicon nitride. This enables the establishment of relatively high Ion/Ioff ratio and improves the reliability of the transistor.

    摘要翻译： 薄膜晶体管包括在栅电极上方的薄膜晶体管体。 氢化薄膜晶体管体以防止晶体管体明显捕获和释放电子。 晶体管本身本身涂覆有上下的氮化硅层，以防止捕获的氢随着时间的推移离开晶体管体。 这是通过在栅电极上沉积二氧化硅层，然后沉积氮化硅层，然后沉积多晶硅层，然后将其蚀刻以形成晶体管体而形成的。 这在阈值调整植入和源极/漏极植入之后被氢化，并随后涂覆有上部氮化硅密封层。 这使得能够建立相对较高的离子/离子比率并提高晶体管的可靠性。

    Formation of polysilicon resistors in the tungsten strapped source/drain/gate process
    78.
    发明授权
    Formation of polysilicon resistors in the tungsten strapped source/drain/gate process 失效
    在钨包扎源/漏极/栅极工艺中形成多晶硅电阻器

    公开(公告)号：US5585302A

    公开(公告)日：1996-12-17

    申请号：US513404

    申请日：1995-08-10

    申请人： Jia Li

    发明人： Jia Li

    IPC分类号： H01L21/02 ,  H01L27/06 ,  H01L21/70

    CPC分类号： H01L28/20 ,  H01L27/0629

    摘要： A semiconductor device having tungsten strapped gate electrodes and source/drain regions and a polysilicon resistor. The gate electrodes and the polysilicon resistors are all formed from the same layer of polysilicon by initially coating the deposited polysilicon layer with an insulating layer and subsequently a layer of phosphorus doped silicon glass. The electrodes and resistor areas are formed by selectively etching the silicon glass and the polysilicon. This leaves the electrode polysilicon and the resistor polysilicon coated with the phosphorous doped glass. Spacers are then provided along the electrode and the glass removed only from above the gate electrode polysilicon leaving the resistor coated with the phosphorus doped silicon glass and silicon nitride. Tungsten then can be selectively deposited upon the gate electrode and along adjacent source and drain regions. This takes advantage of the use of selectively deposited tungsten over gate electrodes and at the same time eliminates the need to deposit separate polysilicon layers for the resistors.

    摘要翻译： 具有钨极限栅电极和源/漏区的半导体器件和多晶硅电阻器。 栅电极和多晶硅电阻均由相同的多晶硅层形成，首先用绝缘层涂覆沉积的多晶硅层，随后用一层磷掺杂的硅玻璃涂覆。 通过选择性地蚀刻硅玻璃和多晶硅来形成电极和电阻器区域。 这留下了涂有磷掺杂玻璃的电极多晶硅和电阻器多晶硅。 然后沿着电极提供间隔物，并且玻璃仅从栅极电极多晶硅上方移除，留下涂覆有磷掺杂硅玻璃和氮化硅的电阻器。 钨然后可以选择性地沉积在栅极电极上并沿着相邻的源极和漏极区域。 这利用了在栅电极上使用选择性沉积的钨，同时消除了为电阻器沉积单独的多晶硅层的需要。