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106 条记录 (耗时 0.029 秒)

    Generating a logic design
    76.
    发明授权
    Generating a logic design 失效

    公开(公告)号：US06983427B2

    公开(公告)日：2006-01-03

    申请号：US09942102

    申请日：2001-08-29

    申请人： William R. Wheeler ,  Matthew J. Adiletta

    发明人： William R. Wheeler ,  Matthew J. Adiletta

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5022

    摘要： A technique to generate a logic design for use in designing an integrated circuit (IC). The technique includes embedding a combinatorial one-dimensional logic block within a two-dimensional schematic presentation to form a unified database. The technique also includes following a set of design capture rules, importing the combinatorial one-dimensional logic block, and notifying a designer when importing the combinatorial data block violates the set of design capture rules.

    Read lock miss control and queue management
    77.
    发明授权
    Read lock miss control and queue management 有权
    读锁定错误控制和队列管理

    公开(公告)号：US06681300B2

    公开(公告)日：2004-01-20

    申请号：US09969436

    申请日：2001-10-02

    申请人： Gilbert Wolrich ,  Daniel Cutter ,  William Wheeler ,  Matthew J. Adiletta ,  Debra Bernstein

    发明人： Gilbert Wolrich ,  Daniel Cutter ,  William Wheeler ,  Matthew J. Adiletta ,  Debra Bernstein

    IPC分类号： G06F1200

    CPC分类号： G06F9/52

    摘要： Managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memory reference request at the end of a read lock miss queue if the read lock memory reference request is requesting access to an unlocked memory location and the read lock miss queue contains at least one read lock memory reference request.

    摘要翻译： 管理对随机存取存储器的存储器访问包括获取读取锁定存储器引用请求并将读取的锁定存储器引用请求放置在读取锁定未命中队列的结尾，如果读取锁定存储器引用请求访问未锁定的存储器位置并读取 锁定未命中队列至少包含一个读锁定存储器引用请求。

    Method and apparatus for gigabit packet assignment for multithreaded packet processing
    79.
    发明授权
    Method and apparatus for gigabit packet assignment for multithreaded packet processing 有权
    用于多线程数据包处理的千兆位数据包分配的方法和装置

    公开(公告)号：US06661794B1

    公开(公告)日：2003-12-09

    申请号：US09474650

    申请日：1999-12-29

    申请人： Gilbert Wolrich ,  Debra Bernstein ,  Matthew J. Adiletta ,  Donald F. Hooper

    发明人： Gilbert Wolrich ,  Debra Bernstein ,  Matthew J. Adiletta ,  Donald F. Hooper

    IPC分类号： H04L1256

    CPC分类号： H04L49/351 ,  H04L49/102 ,  H04L49/352

    摘要： A network processor that has multiple processing elements, each processing element supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads. Each packet may be assigned to a single program thread, two program threads, or a different program thread for segment of data in a packet. For the two program threads, one program thread can be used for header segment processing and the other program thread can be used for handling payload segment(s). Dedicated inputs for ready status and sequence numbers can provide assistance for receiving the packet data over a high speed port. The dedicated inputs are used to monitor ready flags from the high speed ports on a cycle-by-cycle basis. The sequence numbers are used by the assigned threads to maintain ordering of segments within a packet, as well as to order the writes of the complete packets to transmit queues.

    摘要翻译： 具有多个处理元件的网络处理器，每个处理元件支持多个同时的程序线程，并且能够访问接口中的共享资源。 分组数据从段中的高速端口接收，并且每个段被分配给程序线程之一。 每个数据包可以分配给单个程序线程，两个程序线程，或者分组中的数据段的不同程序线程。 对于两个程序线程，一个程序线程可用于头段处理，另一个程序线程可用于处理有效负载段。 准备状态和序列号的专用输入可以帮助通过高速端口接收分组数据。 专用输入用于逐个循环地监视来自高速端口的就绪标志。 分配的线程使用序列号来维护分组中段的排序，以及命令将完整分组写入传送队列。

    Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
    80.
    发明授权
    Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode 有权
    并行多线程处理器，具有执行多个线程的多个微引擎，每个微引擎具有可加载的微代码

    公开(公告)号：US06606704B1

    公开(公告)日：2003-08-12

    申请号：US09387111

    申请日：1999-08-31

    申请人： Matthew J. Adiletta ,  Gilbert Wolrich ,  William Wheeler

    发明人： Matthew J. Adiletta ,  Gilbert Wolrich ,  William Wheeler

    IPC分类号： G06F924

    CPC分类号： G06F9/30076 ,  G06F9/3004 ,  G06F9/3012 ,  G06F9/30127 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F15/8015

    摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.

    摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。