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    Microprocessor with improved instruction cycle using time-compressed fetching
    71.
    发明授权
    Microprocessor with improved instruction cycle using time-compressed fetching 失效
    微处理器使用时间压缩的提取改进了指令周期

    公开(公告)号：US06484252B1

    公开(公告)日：2002-11-19

    申请号：US08488082

    申请日：1995-06-07

    Applicant: Nobuhisa Watanabe

    Inventor： Nobuhisa Watanabe

    IPC: G06F930

    CPC classification number: G06F9/3802 ,  G06F9/321 ,  G06F9/383

    Abstract: A microcomputer includes an instruction decoder and a program counter. The instruction decoder decodes fetched instructions and outputs a control signal ordering execution of the fetched instruction. The control signal from the instruction decoder includes a component controlling fetch cycles which triggers a fetch cycle at the beginning of each instruction cycle to fetch the operand for the instruction currently being executed and midway through each instruction cycle to fetch the OP code for the next instruction. The program counter is responsive to the triggering of each fetch cycle to increment its counter value so as to keep the counter value consistent with the address being accessed in each fetch cycle.

    Abstract translation: 微型计算机包括指令解码器和程序计数器。 指令译码器解码取出的指令，并输出排序执行取指令的控制信号。 来自指令解码器的控制信号包括控制读取周期的部件，其触发在每个指令周期开始时的获取周期，以获取当前正在执行的指令的操作数，并在每个指令周期的中途获取下一个指令的OP代码 。 程序计数器响应于每个读取周期的触发以递增其计数器值，以便使计数值与每个读取周期中被访问的地址保持一致。

    Monochromator and method of manufacturing the same
    73.
    发明授权
    Monochromator and method of manufacturing the same 失效
    单色器及其制造方法

    公开(公告)号：US06229874B1

    公开(公告)日：2001-05-08

    申请号：US09439283

    申请日：1999-11-15

    Applicant: Noriyoshi Sakabe ,  Nobuhisa Watanabe

    Inventor： Noriyoshi Sakabe ,  Nobuhisa Watanabe

    IPC: G21K106

    CPC classification number: G21K1/06 ,  G21K2201/067

    Abstract: A base member obtained by cutting a cylindrical body having a center axial line at a maximum asymmetric angle &agr;0 with respect to a plane orthogonal to the center axial line of cylindrical body is prepared. Next, the thus obtained ellipsoidal asymmetric cut surface of the base member is shaped along a peripheral surface of an imaginary cylindrical body having a radius R0, into an asymmetric cut curved-surface. Then, a monochromator Si crystal is bonded to the asymmetric cut curved-surface of the base member. Both the asymmetric angle and the radius of curvature for a desired wavelength within a wide wavelength range can be simultaneously tuned only by the &phgr;-axis rotation.

    Abstract translation: 准备通过切割具有相对于与圆柱体的中心轴线正交的平面的具有最大不对称角α0的中心轴线的圆柱体获得的基底构件。 接下来，将如此获得的基体的椭圆形不对称切割面沿着具有半径R 0的假想圆筒体的周面成形为非对称切割曲面。 然后，将单色器Si晶体结合到基体的非对称切割曲面上。 在宽波长范围内的所需波长的不对称角和曲率半径都可以仅通过旋转旋转来同时调谐。

    Data bus arrangement with improved speed and timing
    75.
    发明授权
    Data bus arrangement with improved speed and timing 失效
    数据总线布置与改进的速度和时序

    公开(公告)号：US5157772A

    公开(公告)日：1992-10-20

    申请号：US192362

    申请日：1988-05-10

    Applicant: Nobuhisa Watanabe

    Inventor： Nobuhisa Watanabe

    IPC: G06F15/78 ,  G06F13/40

    CPC classification number: G06F13/4077 ,  G06F13/4027

    Abstract: To speed up data transfer, one embodiment of the invention features a transmission gate arrangement which pre-charges and transfers data in internal and external buses with the same timing and which further initializes the internal bus and a device such as an ALU, every bus cycle. A second embodiment speeds the data transfer in the buses by providing two data transfer paths through the interconnected buses and reducing the combined resistances of the internal and external buses.

    Device for use in developing and testing a one-chip microcomputer
    76.
    发明授权
    Device for use in developing and testing a one-chip microcomputer 失效
    用于开发和测试单片机的设备

    公开(公告)号：US5021996A

    公开(公告)日：1991-06-04

    申请号：US370063

    申请日：1989-06-21

    Applicant: Nobuhisa Watanabe

    Inventor： Nobuhisa Watanabe

    IPC: G06F11/22 ,  G06F1/22 ,  G06F11/28 ,  G06F11/36 ,  G06F15/78

    CPC classification number: G06F1/22

    Abstract: A microcomputer universal package has testing terminals and switching circuitry for selecting first and second operations. In the first operation, as an evaluator type, a test device is connected to the testing terminals of the package. In the second operation, as a piggyback type, a rewritable ROM (EPROM) is connected to the testing terminals of the package. The testing terminals are automatically switched for the particular operation by the switching circuitry. Accordingly, the same device can be used as the evaluator type chip and the piggyback-type chip, which reduces the time and the cost of developing the program. In addition, since the piggyback-type chip, the evaluator-type chip, and a mask-type ROM chip can be constructed with the same pin arrangement, the program can be evaluated by the evaluator-type chip in the mask-type ROM mounting board that becomes the final product without requiring an interface board.

    Abstract translation: 微型计算机通用封装具有用于选择第一和第二操作的测试端子和开关电路。 在第一操作中，作为评估器类型，测试装置连接到包装的测试端子。 在第二操作中，作为搭载型，可重写ROM（EPROM）连接到封装的测试端子。 测试终端由切换电路自动切换到特定的操作。 因此，可以使用相同的装置作为评估器型芯片和背负型芯片，这减少了开发程序的时间和成本。 此外，由于搭载式芯片，评估器型芯片和掩模型ROM芯片可以以相同的引脚布置构成，所以可以通过掩模型ROM安装中的评估器型芯片来评估程序 板，成为最终产品，而不需要接口板。

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