System and method of improving blocking immunity of radio frequency transceiver front end

    公开(公告)号:US11196385B2

    公开(公告)日:2021-12-07

    申请号:US16793985

    申请日:2020-02-18

    IPC分类号: H03F1/02 H03F3/21 H03F3/193

    摘要: A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.

    Secure software system for microcontroller or the like and method therefor

    公开(公告)号:US11188656B2

    公开(公告)日:2021-11-30

    申请号:US16047261

    申请日:2018-07-27

    摘要: In one form, a software system includes a first non-transitory computer readable medium storing a source code program, a second computer readable medium, and a compiler. The first non-transitory computer readable medium includes a first function having a return type greater than a native width of a target processor, and a second function that calls the first function and that conditionally branches based on comparing a returned value from the first function to an expected value, wherein the expected value has first and second portions that are not equal to zero and are not equal to each other. The compiler converts the source code program in the first non-transitory computer readable medium into a machine language program for storage in the second computer readable medium. The compiler optimizes the source code program by selectively combining a set of redundant machine language instructions into a smaller set of machine language instructions.

    Neural Network Inference and Training Using A Universal Coordinate Rotation Digital Computer

    公开(公告)号:US20210350221A1

    公开(公告)日:2021-11-11

    申请号:US16866994

    申请日:2020-05-05

    发明人: Javier Elenes

    IPC分类号: G06N3/08 G06F7/544 G06N3/04

    摘要: A system and method of implementing a neural network with a non-linear activation function is disclosed. A Universal Coordinate Rotation Digital Computer (CORDIC) is used to implement the activation function. Advantageously, the CORDIC is also used during training for back propagation. Using a CORDIC, activation functions such as hyperbolic tangent and sigmoid may be implemented without the use of a multiplier. Further, the derivatives of these functions, which are needed for back propagation, can also be implemented using the CORDIC.

    LOW POWER WAKE ON RADIO
    77.
    发明申请

    公开(公告)号:US20210282088A1

    公开(公告)日:2021-09-09

    申请号:US17329496

    申请日:2021-05-25

    IPC分类号: H04W52/02

    摘要: A low power wake on radio circuit detects if an RF signal is present on an input to the wake on radio circuit. An RF sense circuit supplies an RF sense signal indicating whether the RF signal is present on the input. The RF sense signal is used to incrementally turn on digital decode logic to determine if a radio transmission that is unique to the wake on radio circuit has been received. If the unique radio transmission have been received, the wake on radio circuit supplies a wakeup signal to the rest of the system.

    SECURE SCAN ENTRY
    78.
    发明申请

    公开(公告)号:US20210263098A1

    公开(公告)日:2021-08-26

    申请号:US16801447

    申请日:2020-02-26

    摘要: An integrated circuit having a secure domain is disclosed. Circuitry within the integrated circuit is used to select one of a plurality of scan modes. The sequence used to select one of the scan modes also serves to reset all of the flip-flops in the secure domain. In this way, it is impossible for a hacker to use the test modes to shift data from the secure domain out of the integrated circuit. The reset is generated asynchronously upon assertion of a first signal and is terminated upon the assertion of a second signal. The assertion of the second signal also serves to select one of the scan modes. This system cannot be hacked by any method that enters scan mode since it is a hardware based solution.

    MODE SELECTION CIRCUIT FOR LOW-COST INTEGRATED CIRCUITS SUCH AS MICROCONTROLLERS

    公开(公告)号:US20210255678A1

    公开(公告)日:2021-08-19

    申请号:US16791210

    申请日:2020-02-14

    IPC分类号: G06F1/26 G01R19/165 G06F13/40

    摘要: In one form, an integrated circuit includes a negative voltage detector circuit and a logic circuit. The negative voltage detector circuit has a power supply input coupled to a power supply voltage terminal, a ground input coupled to a ground voltage terminal, a first input coupled to a first signal terminal, a second input coupled to a second signal terminal, and an output for providing an enable signal when a voltage on the first signal terminal is less than a voltage on the ground voltage terminal by at least a predetermined amount when a signal on said second signal terminal is in a first predetermined logic state. The logic circuit has an input for receiving the enable signal. The logic circuit changes an operation of the integrated circuit in response to an activation of the enable signal.

    VOLTAGE REGULATOR HAVING MINIMAL FLUCTUATION IN MULTIPLE OPERATING MODES

    公开(公告)号:US20210255653A1

    公开(公告)日:2021-08-19

    申请号:US16793142

    申请日:2020-02-18

    IPC分类号: G05F1/575 G06F1/30

    摘要: In an embodiment, an apparatus includes: an amplifier to compare a reference voltage to a feedback voltage and to output a comparison signal based on the comparison; a first loop circuit coupled to the amplifier to receive the comparison signal and output a first feedback voltage for the amplifier to use as the feedback voltage in a first mode of operation; and a second loop circuit coupled to the amplifier. The second loop circuit may be configured to receive the comparison signal and output a second feedback voltage for the amplifier to use as the feedback voltage in a second mode of operation. The second feedback voltage may be greater than the first feedback voltage, and the second loop circuit may output a regulated voltage based on the comparison signal.