公开(公告)号：US20080315328A1

公开(公告)日：2008-12-25

申请号：US12204072

申请日：2008-09-04

申请人： Shaofeng Yu ,  Shyh-Horng Yang

发明人： Shaofeng Yu ,  Shyh-Horng Yang

IPC分类号： H01L29/78

CPC分类号： H01L21/823892 ,  H01L21/823842 ,  H01L21/823857

摘要： Dopants are implanted at relatively high energies into an unmasked first region of a semiconductor substrate through a thin layer of gate electrode material and a gate dielectric layer. Lower energy dopants are then implanted into the thin layer of gate electrode material. The first region is then masked off, and the process is repeated in a previously masked, but now unmasked, second region of the semiconductor substrate. A second (and usually thicker) layer of gate electrode material is then formed over the thin layer of gate electrode material. The layer of thick gate electrode material, the layer of thin gate electrode material and the layer of gate dielectric material are patterned to form one or more gate structures over the doped regions of the substrate. Source and drain regions are formed in the substrate regions adjacent to the gate structures to establish one or more MOS transistors.

摘要翻译： 掺杂剂通过栅极电极材料和栅极电介质层的薄层以相对高的能量注入到半导体衬底的未屏蔽的第一区域中。 然后将较低能量的掺杂剂注入到栅极电极材料的薄层中。 然后掩蔽第一区域，并且该过程在半导体衬底的先前掩蔽的但现在未掩模的第二区域中重复。 然后在栅电极材料的薄层上形成第二（通常较厚）的栅电极材料层。 将厚栅极电极材料层，薄栅电极材料层和栅极电介质材料层图案化以在衬底的掺杂区域上形成一个或多个栅极结构。 源极和漏极区域形成在与栅极结构相邻的衬底区域中以建立一个或多个MOS晶体管。

公开(公告)号：US20080283941A1

公开(公告)日：2008-11-20

申请号：US12173518

申请日：2008-07-15

申请人： Michael Francis Pas ,  Shaofeng Yu

发明人： Michael Francis Pas ,  Shaofeng Yu

IPC分类号： H01L29/00

CPC分类号： H01L21/823814 ,  H01L21/28097 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

摘要： An integrated circuit includes one or more transistors on or in a semiconductor substrate. At least one of the transistors includes a gate electrode and source and drain structures. The gate electrode has a fully silicided gate electrode layer with a ratio of Ni:Si ranging from about 2:1 to about 3:1. The source and drain structures are located in openings of the substrate and adjacent to the gate electrode. The source and drain structures are filled with SiGe to produce stress in the transistor channel region.

摘要翻译： 集成电路包括在半导体衬底上或半导体衬底中的一个或多个晶体管。 至少一个晶体管包括栅极电极和源极和漏极结构。 栅电极具有完全硅化的栅极电极层，Ni:Si的比例范围为约2:1至约3:1。 源极和漏极结构位于衬底的开口中并且邻近栅电极。 源极和漏极结构充满SiGe以在晶体管沟道区域产生应力。

公开(公告)号：US07396716B2

公开(公告)日：2008-07-08

申请号：US11201924

申请日：2005-08-11

申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Joe G. Tran

发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Joe G. Tran

IPC分类号： H01L21/311

CPC分类号： H01L21/823425 ,  H01L21/28097 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823443 ,  H01L21/823468 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures 230 include sidewall spacers 515 and have a doped region 525 located between them. A protective layer 710 is placed over the capping layer 610 and the doped region 525, and a portion of the protective layer 710 and capping layer 610 that are located over the gate structures are removed to expose a top surface of the gate structures 230. A remaining portion of the protective layer 710 and capping layer 610 remains over the doped region 525. With the top surface of the gate structures 230 exposed, metal is incorporated into the gate structures to form gate electrodes 230.

摘要翻译： 本发明提供一种制造微电子器件的方法。 在一个方面，该方法包括在位于微电子器件衬底210之上的栅极结构230上形成覆盖层610，其中栅极结构230包括侧壁间隔物515并且具有位于它们之间的掺杂区域525。 保护层710放置在覆盖层610和掺杂区域525之上，并且去除位于栅极结构上方的保护层710和覆盖层610的一部分以露出栅极结构230的顶表面。 保护层710和覆盖层610的剩余部分保留在掺杂区域525之上。 在栅极结构230的顶表面暴露的情况下，将金属结合到栅极结构中以形成栅电极230。

公开(公告)号：US07084471B2

公开(公告)日：2006-08-01

申请号：US11122685

申请日：2005-05-04

申请人： Miriam R. Reshotko ,  Shaofeng Yu ,  Bruce A. Block

发明人： Miriam R. Reshotko ,  Shaofeng Yu ,  Bruce A. Block

IPC分类号： H01L29/72

CPC分类号： H01L31/03529 ,  H01L31/0224 ,  H01L31/1085 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A photosensitive device for enabling high speed detection of electromagnetic radiation. The device includes recessed electrodes for providing a generally homogeneous electric field in an active region. Carriers generated in the active region are detected using the recessed electrodes.

摘要翻译： 一种用于实现电磁辐射高速检测的光敏装置。 该装置包括用于在有源区域中提供大致均匀的电场的凹陷电极。 使用凹陷电极检测在有源区域中产生的载体。

公开(公告)号：US08405154B2

公开(公告)日：2013-03-26

申请号：US13167538

申请日：2011-06-23

申请人： Kamel Benaissa ,  Greg C. Baldwin ,  Shaofeng Yu ,  Shashank S. Ekbote

发明人： Kamel Benaissa ,  Greg C. Baldwin ,  Shaofeng Yu ,  Shashank S. Ekbote

IPC分类号： H01L21/70

CPC分类号： H01L21/823437 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66659

摘要： An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.

摘要翻译： 公开了具有相同极性的对称和非对称MOS晶体管的集成电路，其彼此垂直取向，通过使用角度旋转的子植入物的并行晕圈，LDD离子和/或S / D离子注入工艺形成，其使得倾斜 角度，剂量和/或旋转之间的能量。 由倾斜的子植入物形成的注入的光晕，LDD和/或S / D源极和漏极区域可以具有与两种类型的晶体管的栅极重叠或与其分开的不同程度，产生具有两组不同电特性的晶体管。 还公开了同时制造这两种晶体管的工艺。 公开了同时形成对称和不对称晶体管的工艺的具体实施例。

公开(公告)号：US08237234B2

公开(公告)日：2012-08-07

申请号：US13082305

申请日：2011-04-07

申请人： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian S. Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

发明人： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian S. Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

IPC分类号： H01L21/00

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

摘要翻译： 本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料 在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

公开(公告)号：US20110248347A1

公开(公告)日：2011-10-13

申请号：US13167538

申请日：2011-06-23

申请人： Kamel BENAISSA ,  Greg C. BALDWIN ,  Shaofeng YU ,  Shashank S. EKBOTE

发明人： Kamel BENAISSA ,  Greg C. BALDWIN ,  Shaofeng YU ,  Shashank S. EKBOTE

IPC分类号： H01L27/088

CPC分类号： H01L21/823437 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66659

摘要： An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.

摘要翻译： 公开了具有相同极性的对称和非对称MOS晶体管的集成电路，其彼此垂直取向，通过使用角度旋转的子植入物的并行晕圈，LDD离子和/或S / D离子注入工艺形成，其使得倾斜 角度，剂量和/或旋转之间的能量。 由倾斜的子植入物形成的注入的光晕，LDD和/或S / D源极和漏极区域可以具有与两种类型的晶体管的栅极重叠或与其分开的不同程度，产生具有两组不同电特性的晶体管。 还公开了同时制造这两种晶体管的工艺。 公开了同时形成对称和不对称晶体管的工艺的具体实施例。

公开(公告)号：US20110031557A1

公开(公告)日：2011-02-10

申请号：US12908140

申请日：2010-10-20

申请人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

发明人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

摘要： A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.

摘要翻译： 一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。 栅极电介质层形成在PMOS区域和NMOS区域上。 在栅极电介质层上形成原始栅电极层。 栅极掩模层被施加在栅极电极层上。 蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。 为PMOS器件和NMOS器件形成源极和漏极区域。 为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。 在沟槽中形成包括置换栅极的金属，并且完成IC的制造。

公开(公告)号：US20100327374A1

公开(公告)日：2010-12-30

申请号：US12492743

申请日：2009-06-26

申请人： Kamel Benaissa ,  Greg C. Baldwin ,  Shaofeng Yu ,  Shashank S. Ekbote

发明人： Kamel Benaissa ,  Greg C. Baldwin ,  Shaofeng Yu ,  Shashank S. Ekbote

IPC分类号： H01L27/088 ,  H01L21/77 ,  H01L21/265

CPC分类号： H01L21/823437 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66659

摘要： An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed.

摘要翻译： 公开了具有相同极性的对称和非对称MOS晶体管的集成电路，其彼此垂直取向，通过使用角度旋转的子植入物的并行晕圈，LDD离子和/或S / D离子注入工艺形成，其使得倾斜 角度，剂量和/或旋转之间的能量。 由倾斜的子植入物形成的注入的光晕，LDD和/或S / D源极和漏极区域可以具有与两种类型的晶体管的栅极重叠或与其分开的不同程度，产生具有两组不同电性质的晶体管。 还公开了同时制造这两种晶体管的工艺。 公开了同时形成对称和不对称晶体管的工艺的具体实施例。

公开(公告)号：US20090053865A1

公开(公告)日：2009-02-26

申请号：US11841269

申请日：2007-08-20

申请人： Frank Scott Johnson ,  Shaofeng Yu

发明人： Frank Scott Johnson ,  Shaofeng Yu

IPC分类号： H01L21/8238

CPC分类号： H01L29/7847 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6659 ,  H01L29/7833

摘要： Source and drain regions are formed in a first-type semiconductor device. Then, a high tensile stress capping layer is formed over the source and drain regions. A thermal process is then performed to re-crystallize the source and drain regions and to introduce tensile strain into the source and drain regions of the first-type semiconductor device. Afterwards, source and drain regions are formed in a second-type semiconductor device. Then, a high compressive stress capping layer is formed over the source and drain regions of the second-type semiconductor device. A thermal process is performed to re-crystallize the source and drain regions and to introduce compressive strain into the source and drain regions of the second-type semiconductor device.

摘要翻译： 源区和漏区形成在第一类半导体器件中。 然后，在源极和漏极区域上形成高拉伸应力覆盖层。 然后进行热处理以使源极和漏极区域再结晶，并将拉伸应变引入第一类型半导体器件的源极和漏极区域。 之后，源区和漏区形成在第二类半导体器件中。 然后，在第二类型半导体器件的源极和漏极区域上形成高压缩应力覆盖层。 执行热处理以使源区和漏区重新结晶，并将压缩应变引入第二类半导体器件的源区和漏区。