公开(公告)号：US20070186048A1

公开(公告)日：2007-08-09

申请号：US10599170

申请日：2005-03-16

申请人： Ryuta Nakanishi ,  Hazuki Okabayashi ,  Tetsuya Tanaka ,  Tokuzo Kiyohara

发明人： Ryuta Nakanishi ,  Hazuki Okabayashi ,  Tetsuya Tanaka ,  Tokuzo Kiyohara

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： The cache memory in the present invention includes a prediction unit 39 which predicts, based on the progress of the memory access outputted from the memory, a line address which should be prefetched next. The prediction unit 39 includes: a prefetch unit 414 which prefetches data of the predicted line data, from the memory to the cache memory; and a touch unit 415 which sets the predicted line address to the cache entry, as a tag, and validates the valid flag, without loading data from the memory into the cache memory

摘要翻译： 本发明的高速缓冲存储器包括：预测单元39，其基于从存储器输出的存储器访问的进度，预测下一个预取的行地址。 预测单元39包括：预取单元414，其将预测行数据的数据从存储器预取到高速缓冲存储器; 以及触摸单元415，其将预测线路地址设置为高速缓存条目作为标签，并且验证有效标志，而不将数据从存储器加载到高速缓冲存储器

公开(公告)号：US07240309B2

公开(公告)日：2007-07-03

申请号：US10759114

申请日：2004-01-20

申请人： Yoshiyuki Saito ,  Tokuzo Kiyohara

发明人： Yoshiyuki Saito ,  Tokuzo Kiyohara

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/5081

摘要： In a system that provides CAD layout-design information, by having the user acquire information such as circuit design or CAD layout data registered in a database, the user can analyze the acquired information, so there is a possibility that circuit-design or circuit-board-design know-how could be leaked. With this invention, a characteristic-parameter-extraction means extracts characteristic parameters from a position where there is a possibility of the occurrence of poor electrical characteristics due to an influence of the CAD layout of the input CAD layout data. A correction-determination means determines whether or not it is necessary to correct the layout by comparing the characteristic parameters and correction-determination standards that correspond to poor electrical characteristics read from a database. This makes it possible to check the electrical characteristics of the CAD layout without making available to the user the correction-determination standards or determination method.

摘要翻译： 在提供CAD布局设计信息的系统中，通过让用户获取数据库中注册的电路设计或CAD布局数据等信息，用户可以分析获取的信息，因此存在电路设计或电路设计的可能性， 董事会设计专门知识可能会泄漏。 利用本发明，特征参数提取装置从由输入的CAD布局数据的CAD布局的影响可能发生差的电特性的位置提取特征参数。 校正确定装置通过比较与从数据库读取的差的电特性对应的特性参数和校正确定标准来确定是否需要校正布局。 这使得可以在不向用户提供校正确定标准或确定方法的情况下检查CAD布局的电气特性。

公开(公告)号：US07020787B2

公开(公告)日：2006-03-28

申请号：US10323419

申请日：2002-12-18

申请人： Satoshi Takashima ,  Hideshi Nishida ,  Kozo Kimura ,  Tokuzo Kiyohara

发明人： Satoshi Takashima ,  Hideshi Nishida ,  Kozo Kimura ,  Tokuzo Kiyohara

IPC分类号： G06F1/32

CPC分类号： G06F9/30014 ,  G06F7/57

摘要： A microprocessor comprises a calculation unit that (i) includes partial calculation units each operable to perform partial data calculation, and (ii) is operable to perform data calculation on N or less bits, where N is a total number of bits on which the partial calculation units are to perform data calculation. The microprocessor, when having the calculation unit perform data calculation according to an instruction fetched from a memory, controls the partial calculation units depending on a bit width mode selected in terms of a number of bits on which data calculation is to be performed, so as to either (i) have all the partial calculation units operate, or (ii) suspend operation of a predetermined number of the partial calculation units, and have the rest of the partial calculation units operate.

公开(公告)号：US20050238095A1

公开(公告)日：2005-10-27

申请号：US10686237

申请日：2003-10-15

申请人： Kosuke Yoshioka ,  Makoto Hirai ,  Tetsuji Mochida ,  Hiroyuki Oka ,  Hideshi Nishida ,  Tokuzo Kiyohara

发明人： Kosuke Yoshioka ,  Makoto Hirai ,  Tetsuji Mochida ,  Hiroyuki Oka ,  Hideshi Nishida ,  Tokuzo Kiyohara

IPC分类号： G06T3/40 ,  H04N7/12 ,  H04N7/26 ,  H04N7/46 ,  H04N7/50

CPC分类号： G06T3/40 ,  H04N19/16 ,  H04N19/40 ,  H04N19/42 ,  H04N19/59 ,  H04N19/61

摘要： A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.

摘要翻译： 一种用于调整视频数据大小并将调整大小的视频数据输出到再现设备的代码转换器。 再现装置通过重复显示周期和非显示周期交替地再现调整大小的视频数据。 代码转换器包括：调整大小的视频数据的调整大小; 以及控制单元，其使所述调整大小单元将所述视频数据的大小调整为具有第一分辨率的第一视频数据，使得所述再现设备在每个显示周期期间显示一个图像，并且使得调整大小单元在调整大小 将视频数据提供给第一视频数据，将视频数据转换为具有低于第一分辨率的第二分辨率的第二视频数据。

公开(公告)号：US20050102440A1

公开(公告)日：2005-05-12

申请号：US11009607

申请日：2004-12-08

申请人： Nobuo Higaki ,  Tetsuya Tanaka ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura

发明人： Nobuo Higaki ,  Tetsuya Tanaka ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura

IPC分类号： G06F9/38 ,  G06F3/00 ,  G06F9/46 ,  G06F9/48 ,  G06F13/28 ,  G06F15/16 ,  G06F15/167 ,  G06F15/80

CPC分类号： G06F9/4843

摘要： A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

公开(公告)号：US06470376B1

公开(公告)日：2002-10-22

申请号：US09034198

申请日：1998-03-03

申请人： Takaharu Tanaka ,  Kiyoshi Maenobu ,  Kosuke Yoshioka ,  Makoto Hirai ,  Tokuzo Kiyohara

发明人： Takaharu Tanaka ,  Kiyoshi Maenobu ,  Kosuke Yoshioka ,  Makoto Hirai ,  Tokuzo Kiyohara

IPC分类号： G06F900

CPC分类号： G06F9/4881 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3851 ,  H04N19/42 ,  H04N19/61

摘要： The counter 52 is set with an initial value of “1” and is a counter with a maximum value of “4”. This counter 52 increments the count value held by the flip-flop 51 in synchronization with a clock signal so that the count value changes as shown by the progression 1,2,3,4,1,2,3,4. This clock signal is also used by the instruction decode control unit 11 to control the execution of instructions, with the counting by the counter 52 being performed once for each instruction execution performed by the instruction decode control unit 11. The comparator 54 compares the count value counted by the counter 52 with the maximum value “4”, and when the values match, sets the task switching signal chg_task_ex at a “High” value, so that the processing switches to the execution of the next task.

摘要翻译： 计数器52被设置为初始值“1”，并且是具有最大值“4”的计数器。 该计数器52与时钟信号同步地增加由触发器51保持的计数值，使得计数值如进展1,2,3,4,1,2,3,4所示变化。 指令解码控制单元11还使用该时钟信号来控制指令的执行，计数器52对由指令解码控制单元11进行的每个指令执行一次执行一次计数。比较器54将计数值 由具有最大值“4”的计数器52计数，并且当该值匹配时，将任务切换信号chg_task_ex设置为“高”值，使得处理切换到下一任务的执行。

公开(公告)号：US06414608B1

公开(公告)日：2002-07-02

申请号：US09583374

申请日：2000-05-31

申请人： Hideshi Nishida ,  Kosuke Yoshioka ,  Tokuzo Kiyohara

发明人： Hideshi Nishida ,  Kosuke Yoshioka ,  Tokuzo Kiyohara

IPC分类号： H03M740

CPC分类号： H04N19/436 ,  H04N19/61 ,  H04N19/91

摘要： A first bit string extracting unit extracts a first bit string. A first bit length judging unit detects a first codeword from the first bit string. A first decoding unit generates a first run-level pair from the first codeword. A second bit string extracting unit extracts a second bit string. A second bit length judging unit detects a second codeword from the second bit string. A second decoding unit generates a second run-level pair from the second codeword. A first inverse quantizing unit inverse quantizes the first level to obtain a DCT coefficient. A second inverse quantizing unit inverse quantizes the second level to obtain a DCT coefficient. A second buffer controller writes the DCT coefficients and their first buffer addresses into a second buffer. A first buffer controller reads the DCT coefficients and the first buffer addresses from the second buffer and writes the DCT coefficients into a first buffer at the respective first buffer addresses.

摘要翻译： 第一位串提取单元提取第一位串。 第一比特长度判断单元从第一比特串检测第一码字。 第一解码单元从第一码字生成第一游程级对。 第二位串提取单元提取第二位串。 第二位长度判断单元从第二位串检测第二码字。 第二解码单元从第二码字生成第二游程级对。 第一反量化单元逆量化第一电平以获得DCT系数。 第二反量化单元逆量化第二电平以获得DCT系数。 第二缓冲器控制器将DCT系数及其第一缓冲器地址写入第二缓冲器。 第一缓冲器控制器从第二缓冲器读取DCT系数和第一缓冲器地址，并将DCT系数写入相应的第一缓冲器地址的第一缓冲器。

公开(公告)号：US5535358A

公开(公告)日：1996-07-09

申请号：US364277

申请日：1994-12-27

申请人： Kozo Kimura ,  Tokuzo Kiyohara

发明人： Kozo Kimura ,  Tokuzo Kiyohara

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F12/02 ,  G06F13/00

CPC分类号： G06F12/0859

摘要： In cases where a remarked unit of tag addresses set in effective or access state is not registered in a tag section when a reading request is input, an external access is performed, and the remarked unit of tag addresses and other units of tag addresses respectively set in the access state are prepared in a tag entry preparing unit. In cases where a writing request is input to write a piece of updated word data in a remarked unit of data addresses corresponding to the remarked unit of tag addresses before the external access is finished, the state of the remarked tag entry prepared is changed to the effective state, and the updated word data is written in the remarked unit of data addresses of a data storing unit. Because the remarked unit of tag addresses is set in the effective state, the updated word data written in the remarked unit of data addresses is not replaced with a piece of external word data obtained according to the external access when the external access is finished. In cases where any writing request is not input until the external access is finished, the external word data is written in the remarked unit of data addresses, and the state of the remarked unit of tag addresses is changed to the effective state to replace the external word data with a piece of updated word data relating to a following writing request. Therefore, the writing and reading requests can be performed without delaying the writing request.

摘要翻译： 在输入了读取请求时，标签地址设定为有效或访问状态的注释单位未登记在标签区域的情况下，执行外部访问，并且标记地址的标记单位和标签地址的其他单位分别设定 在访问状态下，在标签输入准备单元中准备。 在外部访问完成之前输入写入请求以写入与标记地址的标记单元相对应的数据地址的注释单元中的更新字数据的情况下，准备的标记标签条目的状态被改变为 并且更新的字数据被写入数据存储单元的数据地址的标记单元中。 由于标记地址的标记单位被设置为有效状态，所以在外部访问完成时，写入数据地址的注释单元中的更新后的字数据不被替换为根据外部访问获得的外部字数据。 在外部访问完成之前没有输入任何写入请求的情况下，将外部字数据写入数据地址的注释单元，并将标记地址的标记单元的状态改变为有效状态以替换外部字 具有与以下写入请求有关的更新的字数据的字数据。 因此，可以在不延迟写入请求的情况下执行写入和读取请求。

公开(公告)号：US4967338A

公开(公告)日：1990-10-30

申请号：US137923

申请日：1987-12-28

申请人： Tokuzo Kiyohara ,  Masashi Deguchi

发明人： Tokuzo Kiyohara ,  Masashi Deguchi

IPC分类号： G06F9/34 ,  G06F9/38

CPC分类号： G06F9/3889 ,  G06F9/383

摘要： A central processing unit includes an instruction decoder (1), an operand address computation unit (2), an operand pre-fetch unit (3), a control information buffer (5), an arithmetic unit (4), an instruction fetch unit (6), a chip bus (7), and a bus controller (8). A process relating to the fetch of a memory operand is independent from main pipeline process having an instruction fetching stage, an instruction decoding stage, and an instruction execution stage. As a result, control information (13) in an instruction that the fetch of the memory operand is not required does not pass through the pipeline stage relating to the fetch of the memory operand thereby improving bus band width for memory operand accesses.