公开(公告)号：US20150254093A1

公开(公告)日：2015-09-10

申请号：US14267931

申请日：2014-05-02

Applicant: VIA Technologies, Inc.

Inventor： Kuan-Jui Ho

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45579

Abstract: A system and a method for assigning virtual functions, and a management host thereof are provided. The management host is connected with a computer host through a bridge and has at least one virtual function. A management processor of the management host updates a mapping table according to a virtual function establishing request to assign the at least one virtual function to the computer host according to the mapping table, wherein the management processor determines whether to establish the virtual function according to the mapping table. The management processor transmits a hot-plug event to the corresponding computer host via a switch according to an assignment result and connects the virtual function with the corresponding computer host to dynamically adjust an allocation of the virtual function.

Abstract translation: 提供了一种用于分配虚拟功能的系统和方法及其管理主机。 管理主机通过网桥连接到计算机主机，并具有至少一个虚拟功能。 管理主机的管理处理器根据虚拟功能建立请求更新映射表，以根据映射表将至少一个虚拟功能分配给计算机主机，其中管理处理器根据该映射表确定是否建立虚拟功能 映射表。 管理处理器根据分配结果经由交换机向对应的计算机主机发送热插拔事件，并将虚拟功能与相应的计算机主机相连接以动态地调整虚拟功能的分配。

公开(公告)号：US09118308B1

公开(公告)日：2015-08-25

申请号：US14175220

申请日：2014-02-07

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yeong-Sheng Lee

IPC: H03K5/156 ,  H03K3/017

CPC classification number: H03K3/017 ,  H03K5/1565

Abstract: A duty cycle corrector includes a VCD (Voltage-Controlled Delay) circuit, an edge detector, an SR latch, a mode controller, and a CP (Charge Pump) circuit. The VCD circuit delays an input clock signal for a delay period so as to generate a delay clock signal. The delay period is adjusted according to a CP control voltage. The edge detector detects clock edges of the input clock signal and the delay clock signal so as to correspondingly generate a first clock edge signal and a second clock edge signal. The SR latch generates a toggling signal according to the first clock edge signal and the second clock edge signal. The mode controller generates a mode control voltage. The CP circuit operates in different modes according to the mode control voltage. The CP circuit generates the CP control voltage according to the toggling signal and the mode control voltage.

Abstract translation: 占空比校正器包括VCD（电压控制延迟）电路，边缘检测器，SR锁存器，模式控制器和CP（电荷泵）电路。 VCD电路将输入时钟信号延迟延迟时间，以产生延迟时钟信号。 根据CP控制电压调整延迟时间。 边沿检测器检测输入时钟信号和延迟时钟信号的时钟沿，以便相应地产生第一时钟沿信号和第二时钟沿信号。 SR锁存器根据第一时钟沿信号和第二时钟沿信号产生切换信号。 模式控制器产生模式控制电压。 CP电路根据模式控制电压工作在不同的模式。 CP电路根据切换信号和模式控制电压产生CP控制电压。

公开(公告)号：US09116825B2

公开(公告)日：2015-08-25

申请号：US13910138

申请日：2013-06-05

Applicant: VIA Technologies, Inc.

Inventor： Ming-Han Chung

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/11

CPC classification number: G06F11/10 ,  H03M13/1117 ,  H03M13/116 ,  H03M13/616 ,  H03M13/6502

Abstract: A memory controller is provided. The memory controller includes a memory interface and an encoding module. The memory interface is configured to couple to a memory chip. The encoding module is coupled to the memory interface and includes a shared memory and a parity generation module. The parity generation module is coupled to the shared memory. The parity generation module reads at least one basic vector from the shared memory, determines a dimension of the at least one basic vector, generates a generation matrix according to the at least one basic vector, converts a raw data into a codeword through the generation matrix, and stores the codeword into the memory chip through the memory interface.

Abstract translation: 提供存储器控制器。 存储器控制器包括存储器接口和编码模块。 存储器接口被配置为耦合到存储器芯片。 编码模块耦合到存储器接口并且包括共享存储器和奇偶生成模块。 奇偶生成模块耦合到共享存储器。 奇偶校验生成模块从共享存储器读取至少一个基本向量，确定至少一个基本向量的维度，根据至少一个基本向量生成生成矩阵，通过生成矩阵将原始数据转换为码字 ，并通过存储器接口将码字存储到存储器芯片中。

公开(公告)号：US09111752B1

公开(公告)日：2015-08-18

申请号：US14696785

申请日：2015-04-27

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Ke-Yuan Chen ,  Jyh-Fong Lin

IPC: H02H9/00 ,  H01L27/02

CPC classification number: H01L27/0262 ,  H01L27/0248 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge protection device having a P-type substrate, a common N-well formed in the P-type substrate, a common N-doped region formed in the first common N-well, wherein the common N-doped region is electrically connected to a reference voltage node. The device further has a common P-doped region formed in the common N-well, wherein the common P-doped region surrounds the common N-doped region, the common P-doped region and the common N-well form a common diode, a plurality of peripheral N-wells formed in the P-type substrate and surrounding the common N-well, each of the peripheral N-wells comprising a P-type doped region and a N-type doped region, wherein the P-type doped region is electrically connected to one of a plurality of I/O terminals, and a circular P-doped region formed in the P-type substrate and disposed between the common N-well and the peripheral N-wells, and the circular P-doped region surrounding the common N-well.

Abstract translation: 一种具有P型衬底的静电放电保护器件，在P型衬底中形成的公共N阱，形成在第一公共N阱中的公共N掺杂区域，其中公共N掺杂区域电连接 到参考电压节点。 该器件还具有形成在公共N阱中的公共P掺杂区域，其中公共P掺杂区域围绕公共N掺杂区域，公共P掺杂区域和公共N阱形成公共二极管， 在P型衬底中形成的多个外围N阱并且围绕共用N阱，每个外围N阱包括P型掺杂区和N型掺杂区，其中P型掺杂 区域电连接到多个I / O端子中的一个，以及形成在P型衬底中并设置在公共N阱和外围N阱之间的圆形P掺杂区域，并且环形P掺杂 围绕普通N井的区域。

公开(公告)号：US20150227473A1

公开(公告)日：2015-08-13

申请号：US14463991

申请日：2014-08-20

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Lei FENG

IPC: G06F12/14 ,  G06F21/60

CPC classification number: G06F21/602 ,  G06F21/79 ,  G06F21/85

Abstract: A data scrambling and descrambling technology based on logical addresses. A data storage device with the data scrambling and descrambling technology includes a non-volatile memory and a controller. The controller generates a data scrambling seed according to a logical writing address issued from the host, scrambles the write data issued from the host with the data scrambling seed and then stores the scrambled write data into the non-volatile memory. The controller further generates a data descrambling seed according to a logical reading address issued from the host, and descrambles the read data retrieved from the non-volatile memory by the data descrambling seed. The controller further processes the descrambled read data for data checking and correction.

Abstract translation: 基于逻辑地址的数据加扰和解扰技术。 具有数据加扰和解扰技术的数据存储设备包括非易失性存储器和控制器。 控制器根据从主机发出的逻辑写入地址生成数据加扰种子，用数据加扰种子对从主机发出的写入数据进行加扰，然后将加扰的写入数据存储到非易失性存储器中。 控制器还根据从主机发出的逻辑读取地址产生数据解扰种子，并通过数据解扰种子解扰从非易失性存储器检索的读取数据。 控制器进一步处理解扰的读取数据用于数据检查和校正。

公开(公告)号：US20150134978A1

公开(公告)日：2015-05-14

申请号：US14079299

申请日：2013-11-13

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry

IPC: G06F21/57

CPC classification number: G06F21/572

Abstract: An apparatus including a ROM, a selector, and a detector. The ROM has a partitions, each stored as plaintext, and a encrypted digests, each comprising an encrypted version of a first digest associated with a corresponding one of the partitions. The selector selects one or more partitions responsive to an interrupt. The detector generates the interrupt at a combination of intervals and event occurrences, and accesses the one or more partitions and corresponding one or more encrypted digests upon assertion of the interrupt, and directs a microprocessor to generate corresponding one or more second digests corresponding to the one or more partitions and corresponding one or more decrypted digests corresponding to the one or more encrypted digests using the same algorithms and key that were employed to generate the first message digest and encrypted digests, and compares the one or more second digests with the one or more decrypted digests, and precludes the operation if the one or more second digests and the one or more decrypted digests are not pair wise equal.

Abstract translation: 一种包括ROM，选择器和检测器的装置。 ROM具有每个存储为明文的分区和加密的摘要，每个分组包括与相应的一个分区相关联的第一摘要的加密版本。 选择器响应于中断选择一个或多个分区。 检测器以间隔和事件发生的组合生成中断，并且在断言中访问一个或多个分区和相应的一个或多个加密摘要，并指示微处理器产生对应于该中断的对应的一个或多个第二摘要 或更多分区和对应于使用与生成第一消息摘要和加密摘要相同的算法和密钥的一个或多个加密摘要的对应的一个或多个解密摘要，并将该一个或多个第二摘要与一个或多个 解密的摘要，并且如果一个或多个第二摘要和一个或多个解密的摘要不是成对相等的，则排除操作。

公开(公告)号：US20150134976A1

公开(公告)日：2015-05-14

申请号：US14079145

申请日：2013-11-13

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry

IPC: G06F21/57

CPC classification number: G06F21/572 ,  G06F9/4401 ,  G06F13/24 ,  G06F13/4282 ,  G06F21/554 ,  G06F2221/2107 ,  H04L9/06 ,  H04L9/0618 ,  H04L9/0869 ,  H04L9/3231 ,  H04L9/3242 ,  H04L63/0435 ,  H04L63/0876 ,  H04L63/123

Abstract: An apparatus including a ROM, an event detector, and a tamper detector. The ROM has BIOS contents stored as plaintext, and an encrypted digest. The encrypted digest is an encrypted version of a first digest corresponding to the BIOS contents. The event detector generates an interrupt that interrupts operation of the system upon occurrence of an event. The tamper detector is operatively coupled to the ROM and accesses the BIOS contents and the encrypted digest upon assertion of the interrupt, and directs a microprocessor to generate a second digest corresponding to the BIOS contents and a decrypted digest corresponding to the encrypted digest using the same algorithms and key that were employed to generate the first digest and the encrypted digest, and compares the second message digest with the decrypted message digest, and precludes the operation of the microprocessor if the second digest and the decrypted digest are not equal.

Abstract translation: 一种包括ROM，事件检测器和篡改检测器的装置。 ROM具有存储为明文的BIOS内容和加密摘要。 加密摘要是对应于BIOS内容的第一摘要的加密版本。 事件检测器产生中断事件发生时系统的操作。 篡改检测器可操作地耦合到ROM，并且在断言中访问BIOS内容和加密的摘要，并引导微处理器生成对应于BIOS内容的第二摘要和对应于加密摘要的解密摘要 用于生成第一摘要和加密摘要的算法和密钥，并将第二消息摘要与解密的消息摘要进行比较，并且如果第二摘要和解密的摘要不相等，则排除微处理器的操作。

公开(公告)号：US09018986B2

公开(公告)日：2015-04-28

申请号：US13745991

申请日：2013-01-21

Applicant: VIA Technologies, Inc.

Inventor： Yeong-Sheng Lee

IPC: H03K3/00 ,  G05F3/24

CPC classification number: G05F3/24

Abstract: An output buffer is provided. The output buffer is coupled to a first voltage source providing a first supply voltage and used for generating an output signal at an output terminal according to an input signal. The output buffer includes first and second transistors and a self-bias circuit. The first and second transistors are cascaded between the output terminal and a reference voltage. The self-bias circuit is coupled to the output terminal and the control electrode of the first transistor. When the output buffer does not receive the first supply voltage, the self-bias circuit provides a first bias voltage to the control electrode of the first transistor according to the output signal to decrease voltage differences between the control electrode and the input and output electrodes of the first transistor to be lower than a predetermined voltage.

Abstract translation: 提供输出缓冲区。 输出缓冲器耦合到提供第一电源电压并用于根据输入信号在输出端产生输出信号的第一电压源。 输出缓冲器包括第一和第二晶体管和自偏置电路。 第一和第二晶体管级联在输出端和参考电压之间。 自偏置电路耦合到第一晶体管的输出端和控制电极。 当输出缓冲器没有接收到第一电源电压时，自偏置电路根据输出信号向第一晶体管的控制电极提供第一偏置电压，以减小控制电极与输入和输出电极之间的电压差 第一晶体管低于预定电压。

公开(公告)号：US20150112679A1

公开(公告)日：2015-04-23

申请号：US14499261

申请日：2014-09-29

Applicant: VIA Technologies, Inc.

Inventor： Guo-Feng Zhang

IPC: G10L15/06 ,  G10L15/00

CPC classification number: G10L15/187 ,  G10L15/063 ,  G10L15/14 ,  G10L15/26 ,  G10L2015/0633

Abstract: A method for building a language model, a speech recognition method and an electronic apparatus are provided. The speech recognition method includes the following steps. Phonetic transcriptions of a speech signal are obtained from an acoustic model. Phonetic spellings matching the phonetic transcriptions are obtained according to the phonetic transcriptions and a syllable acoustic lexicon. According to the phonetic spellings, a plurality of text sequences and a plurality of text sequence probabilities are obtained from a language model. Each phonetic spelling is matched to a candidate sentence table; a word probability of each phonetic spelling matching a word in a sentence of the sentence table are obtained; and the word probabilities of the phonetic spellings are calculated so as to obtain the text sequence probabilities. The text sequence corresponding to a largest one of the sequence probabilities is selected as a recognition result of the speech signal.

Abstract translation: 提供了一种构建语言模型，语音识别方法和电子设备的方法。 语音识别方法包括以下步骤。 从声学模型获得语音信号的语音转录。 根据语音转录和音节声学词典获得与语音转录匹配的拼音。 根据语音拼写，从语言模型中获得多个文本序列和多个文本序列概率。 每个语音拼写与候选句表匹配; 获得与句子表的句子中的单词匹配的每个语音拼写的单词概率; 并计算语音拼写的单词概率，以获得文本序列概率。 选择与序列概率中最大的一个对应的文本序列作为语音信号的识别结果。

公开(公告)号：US09009380B2

公开(公告)日：2015-04-14

申请号：US14038717

申请日：2013-09-26

Applicant: VIA Technologies, Inc.

Inventor： Jiin Lai ,  Chin-Sung Hsu ,  Terrance Shiyang Shih ,  Jinkuan Tang ,  Buheng Xu ,  Hui Jiang

IPC: G06F13/36 ,  G06F13/40

CPC classification number: G06F13/4059

Abstract: A universal serial bus (USB) transaction translator is provided along with a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus. At least two buffers are configured to store data. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, with the counting value of the SOF counter being compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves or exceeds the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host.

Abstract translation: 提供通用串行总线（USB）事务转换器以及微帧同步方法。 设备接口经由设备总线耦合到设备，并且主机接口经由主机总线耦合到主机。 至少两个缓冲区被配置为存储数据。 控制器交替地将数据存储在缓冲器中。 使用起始帧（SOF）计数器对SOF数据包进行计数，将SOF计数器的计数值与预定义的值进行比较。 具体地说，当计数值达到或超过预定值时，控制器复位用于发送SOF分组的SOF定时器，使得来自主机的SOF分组和等时时间戳分组（ITP）同时被发送。 此外，控制器根据来自主机的ITP延迟SOF分组的发送一段时间。