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公开(公告)号：US09246479B2
公开(公告)日：2016-01-26
申请号：US14159191
申请日：2014-01-20
Applicant: VIA TECHNOLOGIES, INC.
Inventor： Yeong-Sheng Lee
CPC classification number: H03K5/003 , G05F3/30 , H03F3/45475 , H03F3/45982 , H03F2203/45212
Abstract: A low-offset bandgap circuit including a core bandgap circuit and an offset-cancelling circuit is provided. The low-offset bandgap circuit provides a reference voltage at an output node. The core bandgap circuit includes a core operational amplifier to generate a core current. The offset-cancelling circuit is coupled to two input terminals of the core operational amplifier. The offset-cancelling circuit is configured to generate a compensation current according to the voltages at the two input terminals of the core operational amplifier so as to compensate for an offset voltage of the core operational amplifier. The reference voltage is generated according to the core current and the compensation current.
Abstract translation: 提供了一种包括内核带隙电路和偏移消除电路的低偏移带隙电路。 低偏移带隙电路在输出节点处提供参考电压。 核心带隙电路包括用于产生核心电流的核心运算放大器。 偏移消除电路耦合到核心运算放大器的两个输入端。 偏移消除电路被配置为根据核心运算放大器的两个输入端处的电压产生补偿电流，以补偿核心运算放大器的偏移电压。 参考电压根据磁芯电流和补偿电流产生。
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公开(公告)号：US09118308B1
公开(公告)日：2015-08-25
申请号：US14175220
申请日：2014-02-07
Applicant: VIA TECHNOLOGIES, INC.
Inventor： Yeong-Sheng Lee
CPC classification number: H03K3/017 , H03K5/1565
Abstract: A duty cycle corrector includes a VCD (Voltage-Controlled Delay) circuit, an edge detector, an SR latch, a mode controller, and a CP (Charge Pump) circuit. The VCD circuit delays an input clock signal for a delay period so as to generate a delay clock signal. The delay period is adjusted according to a CP control voltage. The edge detector detects clock edges of the input clock signal and the delay clock signal so as to correspondingly generate a first clock edge signal and a second clock edge signal. The SR latch generates a toggling signal according to the first clock edge signal and the second clock edge signal. The mode controller generates a mode control voltage. The CP circuit operates in different modes according to the mode control voltage. The CP circuit generates the CP control voltage according to the toggling signal and the mode control voltage.
Abstract translation: 占空比校正器包括VCD（电压控制延迟）电路，边缘检测器，SR锁存器，模式控制器和CP（电荷泵）电路。 VCD电路将输入时钟信号延迟延迟时间，以产生延迟时钟信号。 根据CP控制电压调整延迟时间。 边沿检测器检测输入时钟信号和延迟时钟信号的时钟沿，以便相应地产生第一时钟沿信号和第二时钟沿信号。 SR锁存器根据第一时钟沿信号和第二时钟沿信号产生切换信号。 模式控制器产生模式控制电压。 CP电路根据模式控制电压工作在不同的模式。 CP电路根据切换信号和模式控制电压产生CP控制电压。
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公开(公告)号：US09018986B2
公开(公告)日：2015-04-28
申请号：US13745991
申请日：2013-01-21
Applicant: VIA Technologies, Inc.
Inventor： Yeong-Sheng Lee
CPC classification number: G05F3/24
Abstract: An output buffer is provided. The output buffer is coupled to a first voltage source providing a first supply voltage and used for generating an output signal at an output terminal according to an input signal. The output buffer includes first and second transistors and a self-bias circuit. The first and second transistors are cascaded between the output terminal and a reference voltage. The self-bias circuit is coupled to the output terminal and the control electrode of the first transistor. When the output buffer does not receive the first supply voltage, the self-bias circuit provides a first bias voltage to the control electrode of the first transistor according to the output signal to decrease voltage differences between the control electrode and the input and output electrodes of the first transistor to be lower than a predetermined voltage.
Abstract translation: 提供输出缓冲区。 输出缓冲器耦合到提供第一电源电压并用于根据输入信号在输出端产生输出信号的第一电压源。 输出缓冲器包括第一和第二晶体管和自偏置电路。 第一和第二晶体管级联在输出端和参考电压之间。 自偏置电路耦合到第一晶体管的输出端和控制电极。 当输出缓冲器没有接收到第一电源电压时，自偏置电路根据输出信号向第一晶体管的控制电极提供第一偏置电压，以减小控制电极与输入和输出电极之间的电压差 第一晶体管低于预定电压。
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4.发明授权公开(公告)号：US08952734B2
公开(公告)日：2015-02-10
申请号：US13850666
申请日：2013-03-26
Applicant: Via Technologies, Inc.
Inventor： Yeong-Sheng Lee
CPC classification number: H03L7/14 , H03L7/0816 , H03L7/0891 , H03L7/099 , H04L27/00
Abstract: A signal generation device is provided to generate an output signal with constant frequency. The signal generation device includes a frequency-control circuit and a voltage-controlled delay line. The frequency-control circuit includes a pulse generator, generating a reference pulse signal according to a transition of the reference signal and a comparison pulse signal according to a transition of the comparison result signal, to re-shape the reference signal and the comparison result signal into narrow pulses suitable for clocking and resetting flip-flops.
Abstract translation: 提供信号发生装置以产生具有恒定频率的输出信号。 信号发生装置包括频率控制电路和电压控制延迟线。 频率控制电路包括脉冲发生器，根据比较结果信号的转变，根据参考信号的转变和比较脉冲信号产生参考脉冲信号，以重新形成参考信号和比较结果信号 转换成适合时钟和复位触发器的窄脉冲。
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公开(公告)号：US09083584B2
公开(公告)日：2015-07-14
申请号：US13968705
申请日：2013-08-16
Applicant: VIA Technologies, Inc.
Inventor： Yeong-Sheng Lee
CPC classification number: H04L25/085 , H04L25/0276
Abstract: The present disclosure provides systems and methods for compensating channel modulation effects. Some embodiments comprise a differential switching circuit, a common mode modulation circuit, and a current compensation circuit. The current compensation circuit compensates for channel modulation effects.
Abstract translation: 本公开提供了用于补偿信道调制效应的系统和方法。 一些实施例包括差分开关电路，共模调制电路和电流补偿电路。 电流补偿电路补偿通道调制效应。
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Patent Agency Ranking
公开(公告)号：US09000846B2
公开(公告)日：2015-04-07
申请号：US13939325
申请日：2013-07-11
Applicant: VIA Technologies, Inc.
Inventor： Yeong-Sheng Lee
CPC classification number: H03F3/345 , H03F3/45183 , H03F2200/91 , H03F2203/45674
Abstract: Some embodiments of the system comprise a current mirror with two switches (a first switch and a second switch) and two compensation circuits (a first compensation circuit and a second compensation circuit). In one embodiment, the first compensation circuit adjusts a drain voltage of the second switch based on a drain voltage of the first switch, and the second compensation circuit adjusts a current through the first switch based on the drain voltage of the second switch.
Abstract translation: 该系统的一些实施例包括具有两个开关（第一开关和第二开关）和两个补偿电路（第一补偿电路和第二补偿电路）的电流镜。 在一个实施例中，第一补偿电路基于第一开关的漏极电压来调节第二开关的漏极电压，并且第二补偿电路基于第二开关的漏极电压来调节通过第一开关的电流。
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7.发明授权Low voltage differential signal driving circuit and electronic device compatible with wired transmission 有权低电压差分信号驱动电路和电子设备兼容有线传输公开(公告)号：US08952725B2
公开(公告)日：2015-02-10
申请号：US13685131
申请日：2012-11-26
Applicant: Via Technologies, Inc.
Inventor： Yeong-Sheng Lee , Kuen-Chir Wang
IPC: H03K19/094 , H03K17/04 , H03K17/00 , H03K19/0185 , H04L25/02
CPC classification number: H03K17/04 , H03K17/002 , H03K19/018528 , H04L25/0272 , H04L25/0278
Abstract: A low voltage differential signal driving circuit including positive and negative differential output terminals, an automatic level selector, an output level detector and a transition accelerator. The positive and negative differential output terminals provide a transmission interface with a differential output signal for transmission of a data signal. The automatic level selector outputs a reference voltage corresponding to the transmission interface. The output level detector generates a low-high (or high-low) transition acceleration control signal based on the data signal, the reference voltage, and VTXP signal at the positive differential output terminal (or VTXN signal at the negative differential output terminal). In accordance with the low-high (or high-low) transition acceleration control signal, the transition accelerator couples the positive (or negative) differential output terminal to a high voltage source and couples the negative (or positive) differential output terminal to a low voltage source to accelerate transition of the differential output signal.
Abstract translation: 包括正和负差分输出端子的低电压差分信号驱动电路，自动电平选择器，输出电平检测器和转换加速器。 正和负差分输出端子提供具有用于传输数据信号的差分输出信号的传输接口。 自动电平选择器输出与传输接口对应的参考电压。 输出电平检测器基于正差分输出端子（或负差分输出端子处的VTXN信号）的数据信号，参考电压和VTXP信号产生低电平（或高 - 低）转换加速控制信号。 根据低 - 高（或高 - 低）转换加速度控制信号，转换加速器将正（或负）差分输出端耦合到高电压源，并将负（或正）差分输出端耦合到低电平 电压源加速差分输出信号的转换。
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公开(公告)号：US08836382B1
公开(公告)日：2014-09-16
申请号：US13892570
申请日：2013-05-13
Applicant: Via Technologies, Inc.
Inventor： Yeong-Sheng Lee
CPC classification number: H03K17/162
Abstract: A driving circuit is provided. The driving circuit has: a level shifter configured to receive a reference voltage and an input signal at a first voltage to generate a second voltage; an differential amplifier, coupled to the level shifter, configured to receive the second voltage and an output signal to provide an operating voltage, wherein the differential amplifier is supplied by a first power source at a third voltage; and an output stage, coupled to the differential amplifier, configured to receive the input signal and the operating voltage for switching the output signal, wherein the first voltage is smaller than the third voltage, and the output signal has a fourth voltage between the first voltage and the third voltage.
Abstract translation: 提供驱动电路。 驱动电路具有：电平移位器，被配置为以第一电压接收参考电压和输入信号以产生第二电压; 耦合到电平移位器的差分放大器，被配置为接收第二电压和输出信号以提供工作电压，其中差分放大器由第三电压的第一电源提供; 以及耦合到差分放大器的输出级，被配置为接收输入信号和用于切换输出信号的工作电压，其中第一电压小于第三电压，并且输出信号具有第一电压 和第三电压。
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公开(公告)号：US20150049839A1
公开(公告)日：2015-02-19
申请号：US13968705
申请日：2013-08-16
Applicant: VIA Technologies, Inc.
Inventor： Yeong-Sheng Lee
IPC: H04L25/08
CPC classification number: H04L25/085 , H04L25/0276
Abstract: The present disclosure provides systems and methods for compensating channel modulation effects. Some embodiments comprise a differential switching circuit, a common mode modulation circuit, and a current compensation circuit. The current compensation circuit compensates for channel modulation effects.
Abstract translation: 本公开提供了用于补偿信道调制效应的系统和方法。 一些实施例包括差分开关电路，共模调制电路和电流补偿电路。 电流补偿电路补偿通道调制效应。
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公开(公告)号：US08890627B2
公开(公告)日：2014-11-18
申请号：US13943174
申请日：2013-07-16
Applicant: Via Technologies, Inc.
Inventor： Yeong-Sheng Lee
CPC classification number: H03B1/00 , H03K3/0322
Abstract: A voltage controlled oscillator generating an oscillation signal according to a first control signal without a silent region. The voltage controlled oscillator includes a control signal adjuster and a plurality of delay cells. The control signal adjuster receives the first control signal and generates a second and a third control signal according to the first control signal. The voltage level of the third control signal is higher than that of the second control signal and the voltage level of the second control signal is higher than that of the first control signal. The plurality of delay cells are ring-connected and controlled by the first, the second, and the third control signals to generate the oscillation signal. Each delay cell includes three sets of current generation transistors. The three sets of current generation transistors are separately controlled by the three different control signals.
Abstract translation: 压控振荡器根据没有静音区域的第一控制信号产生振荡信号。 压控振荡器包括控制信号调节器和多个延迟单元。 控制信号调节器接收第一控制信号，并根据第一控制信号产生第二和第三控制信号。 第三控制信号的电压电平高于第二控制信号的电压电平，第二控制信号的电压电平高于第一控制信号的电压电平。 多个延迟单元由第一，第二和第三控制信号环形连接和控制，以产生振荡信号。 每个延迟单元包括三组电流产生晶体管。 三组电流发生晶体管由三种不同的控制信号分别控制。
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