公开(公告)号：US20240109769A1

公开(公告)日：2024-04-04

申请号：US18538503

申请日：2023-12-13

Applicant: Xintec Inc.

Inventor： Wei-Luen SUEN ,  Jiun-Yen LAI ,  Hsing-Lung SHEN ,  Tsang-Yu LIU

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0067 ,  B81C1/00317 ,  B81B2203/0353 ,  B81C2201/0125 ,  B81C2201/0132 ,  B81C2201/0194

Abstract: A chip package includes a semiconductor substrate and a metal layer. The semiconductor substrate has an opening and a sidewall surrounding the opening, in which an upper portion of the sidewall is a concave surface. The semiconductor substrate is made of a material including silicon. The metal layer is located on the semiconductor substrate. The metal layer has plural through holes above the opening to define a MEMS (Microelectromechanical system) structure, in which the metal layer is made of a material including aluminum.

公开(公告)号：US20230361144A1

公开(公告)日：2023-11-09

申请号：US18304325

申请日：2023-04-20

Applicant: Xintec Inc.

Inventor： Wei-Ming CHIEN ,  Po-Han LEE ,  Tsang Yu LIU ,  Joey LAI

IPC: H01L27/146

CPC classification number: H01L27/14632 ,  H01L27/14621 ,  H01L27/14623

Abstract: A chip package includes a light transmissive sheet, a chip, a bonding layer, and an insulating layer. The light transmissive sheet has a protruding portion. A first surface of the chip faces toward the light transmissive sheet and has a sensing area. The bonding layer is located between the chip and the light transmissive sheet. The sum of a thickness of the chip and a thickness of the bonding layer is greater than or equal to a thickness of the light transmissive sheet. A protruding portion of the light transmissive sheet protrudes from a sidewall of the chip and a sidewall of the bonding layer. The insulating layer extends from a second surface of the chip to the protruding portion of the light transmissive sheet along the sidewall of the chip and the sidewall of the bonding layer.

公开(公告)号：US20230049126A1

公开(公告)日：2023-02-16

申请号：US17980507

申请日：2022-11-03

Applicant: XINTEC INC.

Inventor： Chia-Ming CHENG ,  Shu-Ming CHANG

IPC: H01L23/552 ,  H01L23/66 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L21/56

Abstract: A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

公开(公告)号：US20220285423A1

公开(公告)日：2022-09-08

申请号：US17683917

申请日：2022-03-01

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Shu-Ming CHANG ,  Chaung-Lin LAI

IPC: H01L27/146 ,  H01L23/544

Abstract: Chip packages and methods for forming the same are provided. The method includes providing a substrate having upper and lower surfaces, and having a chip region and a scribe-line region surrounding the chip region. The substrate has a dielectric layer on its upper surface. A masking layer is formed over the substrate to cover the dielectric layer. The masking layer has a first opening exposing the dielectric layer and extending in the extending direction of the scribe-line region to surround the chip region. An etching process is performed on the dielectric layer directly below the first opening, to form a second opening that is in the dielectric layer directly below the first opening. The masking layer is removed to expose the dielectric layer having the second opening. A dicing process is performed on the substrate through the second opening.

公开(公告)号：US20220157762A1

公开(公告)日：2022-05-19

申请号：US17588185

申请日：2022-01-28

Applicant: XINTEC INC.

Inventor： Jiun-Yen LAI ,  Chia-Hsiang CHEN

IPC: H01L23/00 ,  H01L23/48

Abstract: A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

公开(公告)号：US11310904B2

公开(公告)日：2022-04-19

申请号：US16663366

申请日：2019-10-25

Applicant: XINTEC INC.

Inventor： Tsang-Yu Liu ,  Po-Han Lee ,  Wei-Ming Chien

IPC: H05K1/02 ,  H05K1/03 ,  H01L23/00

Abstract: A chip package includes a high voltage withstanding substrate and a device chip. The high voltage withstanding substrate has a main body, a functional layer, and a grounding layer. The main body has a top surface, a bottom surface opposite the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The functional layer is located on the top surface. The grounding layer covers the bottom surface and the sidewall. The device chip is located on the functional layer, and has a grounding pad that faces the main body. The grounding pad is electrically connected to the grounding layer in the through hole.

公开(公告)号：US11164853B1

公开(公告)日：2021-11-02

申请号：US17170482

申请日：2021-02-08

Applicant: XINTEC INC.

Inventor： Chia-Ming Cheng ,  Shu-Ming Chang

IPC: H01L23/495 ,  H01L25/16 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  B81B7/00

Abstract: A chip package includes a first chip, a second chip, a first molding compound, and a first distribution line. The second chip vertically or laterally overlaps the first chip. The second chip has a conductive pad. The first molding compound covers the first and second chips, and surrounds the second chip. The first molding compound has a first through hole. The conductive pad is in the first through hole. The first distribution line is located on a surface of the first molding compound facing away from the second chip, and electrically connects the conductive pad in the first through hole.

公开(公告)号：US20210210445A1

公开(公告)日：2021-07-08

申请号：US17140952

申请日：2021-01-04

Applicant: XINTEC INC.

Inventor： Chia-Ming CHENG ,  Shu-Ming CHANG

IPC: H01L23/66 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56

Abstract: A chip package includes a semiconductor substrate, a first light-transmissive sheet, a second light-transmissive sheet, a first antenna layer, and a redistribution layer. The first light-transmissive sheet is disposed over the semiconductor substrate, and has a top surface facing away from semiconductor substrate and an inclined sidewall adjacent to the top surface. The second light-transmissive sheet is disposed over the first light-transmissive sheet. The first antenna layer is disposed between the first light-transmissive sheet and the second light-transmissive sheet. The redistribution layer is disposed on the inclined sidewall of the first light-transmissive sheet, and is in contact with an end of the first antenna layer.

公开(公告)号：US11056427B2

公开(公告)日：2021-07-06

申请号：US16576714

申请日：2019-09-19

Applicant: XINTEC INC.

Inventor： Kuei-Wei Chen ,  Chia-Ming Cheng

IPC: H01L23/522 ,  H01L23/48

Abstract: A chip package includes a substrate, first and second dielectric layers, first and second metal layers, and first conductive vias. The first dielectric layer is on a bottom surface of the substrate. The first metal layer is on a bottom surface of the first dielectric layer. The first metal layer has first sections, and every two adjacent first sections have a gap therebetween. The second dielectric layer is on a bottom surface of the first metal layer and the bottom surface of the first dielectric layer. The second metal layer is on a bottom surface of the second dielectric layer, and has second sections respectively aligned with the gaps. Two sides of the second section respectively overlap two adjacent first sections. The first conductive via is in the second dielectric layer and in electrical contact with the first and second sections.

公开(公告)号：US20210032096A1

公开(公告)日：2021-02-04

申请号：US16941465

申请日：2020-07-28

Applicant: XINTEC INC.

Inventor： Tsang-Yu LIU ,  Chaung-Lin LAI ,  Shu-Ming CHANG

IPC: B81B7/00 ,  B81C1/00

Abstract: A chip package includes a first die, a second die, a molding material, and a redistribution layer. The first die includes a first conductive pad. The second die is disposed on the first die and includes a second conductive pad. The molding material covers the first die and the second die. The molding material includes a top portion, a bottom portion, and an inclined portion adjoins the top portion and the bottom portion. The top portion is located on the second die, and the bottom portion is located on the first die. The redistribution layer is disposed along the top portion, the inclined portion, and the bottom portion. The redistribution layer is electrically connected to the first conductive pad and the second conductive pad.