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    Chip package
    1.
    发明授权
    Chip package 有权

    公开(公告)号：US11056427B2

    公开(公告)日：2021-07-06

    申请号：US16576714

    申请日：2019-09-19

    申请人： XINTEC INC.

    发明人： Kuei-Wei Chen ,  Chia-Ming Cheng

    IPC分类号： H01L23/522 ,  H01L23/48

    摘要： A chip package includes a substrate, first and second dielectric layers, first and second metal layers, and first conductive vias. The first dielectric layer is on a bottom surface of the substrate. The first metal layer is on a bottom surface of the first dielectric layer. The first metal layer has first sections, and every two adjacent first sections have a gap therebetween. The second dielectric layer is on a bottom surface of the first metal layer and the bottom surface of the first dielectric layer. The second metal layer is on a bottom surface of the second dielectric layer, and has second sections respectively aligned with the gaps. Two sides of the second section respectively overlap two adjacent first sections. The first conductive via is in the second dielectric layer and in electrical contact with the first and second sections.

    Manufacturing method of chip package and chip package
    3.
    发明授权
    Manufacturing method of chip package and chip package 有权

    公开(公告)号：US11705368B2

    公开(公告)日：2023-07-18

    申请号：US17373773

    申请日：2021-07-13

    申请人： XINTEC INC.

    发明人： Chia-Sheng Lin ,  Hui-Hsien Wu ,  Jian-Hong Chen ,  Tsang-Yu Liu ,  Kuei-Wei Chen

    IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L21/02

    CPC分类号： H01L21/76894 ,  H01L21/02013 ,  H01L24/94

    摘要： A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

    Manufacturing method of chip package and chip package
    5.
    发明授权
    Manufacturing method of chip package and chip package 有权

    公开(公告)号：US11942563B1

    公开(公告)日：2024-03-26

    申请号：US18327875

    申请日：2023-06-01

    申请人： XINTEC INC.

    发明人： Chia-Sheng Lin ,  Hui-Hsien Wu ,  Jian-Hong Chen ,  Tsang-Yu Liu ,  Kuei-Wei Chen

    IPC分类号： H01L31/0352 ,  H01L31/02

    CPC分类号： H01L31/03529 ,  H01L31/02005

    摘要： A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

    Chip package with substrate having first opening surrounded by second opening and method for forming the same
    6.
    发明授权
    Chip package with substrate having first opening surrounded by second opening and method for forming the same 有权

    公开(公告)号：US11450697B2

    公开(公告)日：2022-09-20

    申请号：US16581594

    申请日：2019-09-24

    申请人： XINTEC INC.

    发明人： Kuei-Wei Chen ,  Chia-Ming Cheng ,  Chia-Sheng Lin

    IPC分类号： H01L27/146

    摘要： A chip package including a substrate, a first conductive structure, and an electrical isolation structure is provided. The substrate has a first surface and a second surface opposite the first surface), and includes a first opening and a second opening surrounding the first opening. The substrate includes a sensor device adjacent to the first surface. A first conductive structure includes a first conductive portion in the first opening of the substrate, and a second conductive portion over the second surface of the substrate. An electrical isolation structure includes a first isolation portion in the second opening of the substrate, and a second isolation portion extending from the first isolation portion and between the second surface of the substrate and the second conductive portion. The first isolation portion surrounds the first conductive portion.

    MANUFACTURING METHOD OF CHIP PACKAGE AND CHIP PACKAGE
    7.
    发明申请
    MANUFACTURING METHOD OF CHIP PACKAGE AND CHIP PACKAGE 有权

    公开(公告)号：US20210343591A1

    公开(公告)日：2021-11-04

    申请号：US17373773

    申请日：2021-07-13

    申请人： XINTEC INC.

    发明人： Chia-Sheng Lin ,  Hui-Hsien Wu ,  Jian-Hong Chen ,  Tsang-Yu Liu ,  Kuei-Wei Chen

    IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L21/02

    摘要： A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.

    Manufacturing method of chip package and chip package
    8.
    发明授权
    Manufacturing method of chip package and chip package 有权

    公开(公告)号：US11121031B2

    公开(公告)日：2021-09-14

    申请号：US16668570

    申请日：2019-10-30

    申请人： XINTEC INC.

    发明人： Chia-Sheng Lin ,  Hui-Hsien Wu ,  Jian-Hong Chen ,  Tsang-Yu Liu ,  Kuei-Wei Chen

    IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L21/02

    摘要： A manufacturing method of a chip package includes patterning a wafer to form a scribe trench, in which a light-transmissive function layer below the wafer is in the scribe trench, the light-transmissive function layer is between the wafer and a carrier, and a first included angle is formed between an outer wall surface and a surface of the wafer facing the light-transmissive function layer; cutting the light-transmissive function layer and the carrier along the scribe trench to form a chip package that includes a chip, the light-transmissive function layer, and the carrier; and patterning the chip to form an opening, in which the light-transmissive function layer is in the opening, a second included angle is formed between an inner wall surface of the chip and a surface of the chip facing the light-transmissive function layer, and is different from the first included angle.