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    Chip package and manufacturing method thereof
    1.
    发明授权
    Chip package and manufacturing method thereof 有权

    公开(公告)号：US11164853B1

    公开(公告)日：2021-11-02

    申请号：US17170482

    申请日：2021-02-08

    Applicant: XINTEC INC.

    Inventor： Chia-Ming Cheng ,  Shu-Ming Chang

    IPC: H01L23/495 ,  H01L25/16 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  B81B7/00

    Abstract: A chip package includes a first chip, a second chip, a first molding compound, and a first distribution line. The second chip vertically or laterally overlaps the first chip. The second chip has a conductive pad. The first molding compound covers the first and second chips, and surrounds the second chip. The first molding compound has a first through hole. The conductive pad is in the first through hole. The first distribution line is located on a surface of the first molding compound facing away from the second chip, and electrically connects the conductive pad in the first through hole.

    Chip package
    2.
    发明授权
    Chip package 有权

    公开(公告)号：US11056427B2

    公开(公告)日：2021-07-06

    申请号：US16576714

    申请日：2019-09-19

    Applicant: XINTEC INC.

    Inventor： Kuei-Wei Chen ,  Chia-Ming Cheng

    IPC: H01L23/522 ,  H01L23/48

    Abstract: A chip package includes a substrate, first and second dielectric layers, first and second metal layers, and first conductive vias. The first dielectric layer is on a bottom surface of the substrate. The first metal layer is on a bottom surface of the first dielectric layer. The first metal layer has first sections, and every two adjacent first sections have a gap therebetween. The second dielectric layer is on a bottom surface of the first metal layer and the bottom surface of the first dielectric layer. The second metal layer is on a bottom surface of the second dielectric layer, and has second sections respectively aligned with the gaps. Two sides of the second section respectively overlap two adjacent first sections. The first conductive via is in the second dielectric layer and in electrical contact with the first and second sections.

    Power MOSFET package
    4.
    发明授权
    Power MOSFET package 有权
    功率MOSFET封装

    公开(公告)号：US08766431B2

    公开(公告)日：2014-07-01

    申请号：US13828537

    申请日：2013-03-14

    Applicant: Xintec Inc.

    Inventor： Baw-Ching Perng ,  Ying-Nan Wen ,  Shu-Ming Chang ,  Ching-Yu Ni ,  Yun-Ji Hsieh ,  Wei-Ming Chen ,  Chia-Lun Tsai ,  Chia-Ming Cheng

    IPC: H01L23/04

    CPC classification number: H01L29/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/492 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2224/05099

    Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.

    Abstract translation: 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

    Chip package including substrate inclined sidewall and redistribution line
    5.
    发明授权
    Chip package including substrate inclined sidewall and redistribution line 有权

    公开(公告)号：US11521938B2

    公开(公告)日：2022-12-06

    申请号：US17140964

    申请日：2021-01-04

    Applicant: XINTEC INC.

    Inventor： Chia-Ming Cheng ,  Shu-Ming Chang

    IPC: H01L23/552 ,  H01L23/528 ,  H01L23/66 ,  H01L21/56 ,  H01L23/31 ,  H01L23/522

    Abstract: A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

    Chip package and manufacturing method thereof
    6.
    发明授权
    Chip package and manufacturing method thereof 有权

    公开(公告)号：US10833118B2

    公开(公告)日：2020-11-10

    申请号：US15001065

    申请日：2016-01-19

    Applicant: XINTEC INC.

    Inventor： Tsang-Yu Liu ,  Chia-Ming Cheng

    IPC: H01L27/146

    Abstract: A manufacturing method of a chip package includes the following steps. A light transmissive substrate is bonded to a first surface of a wafer, such that a dam element between the light transmissive substrate and the wafer covers a conductive pad of the wafer. A second surface of the wafer facing away from the first surface is etched, such that a hollow region and a trench selectively communicated with the hollow region are synchronously formed in the wafer. A first isolation layer on the conductive pad is etched to expose the conductive pad through the hollow region.

    Chip package and method for forming the same
    9.
    发明授权
    Chip package and method for forming the same 有权
    芯片封装及其形成方法

    公开(公告)号：US09349710B2

    公开(公告)日：2016-05-24

    申请号：US14504319

    申请日：2014-10-01

    Applicant: XINTEC INC.

    Inventor： Chien-Hui Chen ,  Tsang-Yu Liu ,  Chun-Wei Chang ,  Chia-Ming Cheng

    IPC: H01L21/50 ,  H01L25/065 ,  H01L21/683 ,  H01L23/00

    CPC classification number: H01L25/0655 ,  H01L21/6835 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for forming a chip package is provided. A first substrate is provided. A second substrate is attached on the first substrate, wherein the second substrate has a plurality of rectangular chip regions separated by a scribed-line region. A portion of the second substrate corresponding to the scribed-line region is removed to form a plurality of chips on the first substrate, wherein at least one bridge portion is formed between adjacent chips. A chip package formed by the method is also provided.

    Abstract translation: 提供一种形成芯片封装的方法。 提供第一基板。 第二衬底附接在第一衬底上，其中第二衬底具有由划线区域分隔的多个矩形芯片区域。 去除对应于划线区域的第二衬底的一部分，以在第一衬底上形成多个芯片，其中在相邻芯片之间形成至少一个桥接部分。 还提供了通过该方法形成的芯片封装。

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