公开(公告)号：US09524261B2

公开(公告)日：2016-12-20

申请号：US13724955

申请日：2012-12-21

Applicant: Apple Inc.

Inventor： Gurjeet S. Saund ,  Harshavardhan Kaushikkar ,  Benjamin K. Dodge

IPC: G06F13/00 ,  G06F3/00 ,  G06F13/38 ,  G06F13/28 ,  H04L12/801

CPC classification number: G06F13/385 ,  G06F13/28 ,  H04L47/10

Abstract: Systems and methods for preventing excessive buffering of transactions in a coherence point. The coherence point uses a lookahead mechanism to determine if there are enough credits from the memory controller for forwarding the outstanding transactions stored in the IRQ. If there are not enough credits, then the coherence point prevents the switch fabric from forwarding additional transactions to the coherence point. By preventing excessive buffering in the IRQ, the QoS-based ordering of transactions performed by the switch fabric is preserved.

Abstract translation: 在一致性点防止交易过度缓冲的系统和方法。 相干点使用前瞻机制来确定存储器控制器中是否有足够的信用来转发存储在IRQ中的未完成事务。 如果没有足够的积分，则相干点可以防止交换结构将附加事务转发到相干点。 通过防止IRQ中的过度缓冲，交换结构执行的事务的基于QoS的排序得以保留。

公开(公告)号：US20150143044A1

公开(公告)日：2015-05-21

申请号：US14081549

申请日：2013-11-15

Applicant: APPLE INC.

Inventor： Manu Gulati ,  Harshavardhan Kaushikkar ,  Gurjeet S. Saund ,  Wei-Han Lien ,  Gerard R. Williams, III ,  Sukalpa Biswas ,  Brian P. Lilly ,  Shinye Shiu

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0822 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity, the agent's private cache can be shared with other agents. When a requesting agent generates a memory request and the memory request misses in the memory cache, the memory cache can allocate the memory request in a separate agent's cache rather than allocating the memory request in the memory cache.

Abstract translation: 与SoC中的其他代理程序共享代理的私有缓存的系统，处理器和方法。 SoC中的许多代理除了SoC的共享缓存和内存之外还有一个专用缓存。 如果代理的处理器关闭或以小于满容量运行，代理的私有缓存可以与其他代理共享。 当请求代理产生存储器请求并且存储器请求丢失在存储器高速缓存中时，存储器高速缓存可以在单独的代理的高速缓存中分配存储器请求，而不是在存储器高速缓存中分配存储器请求。

公开(公告)号：US20150006803A1

公开(公告)日：2015-01-01

申请号：US13928636

申请日：2013-06-27

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Muditha Kanchana ,  Odutola O. Ewedemi

IPC: G06F12/08

CPC classification number: G06F12/0815

Abstract: An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a single-port memory, a dual-port memory, and a control circuit. The single-port memory may be store tag information associated with a cache memory, and the dual-port memory may be configured to store state information associated with the cache memory. The control circuit may be configured to receive a request which includes a tag address, access the tag and state information stored in the single-port memory and the dual-port memory, respectively, dependent upon the received tag address. A determination of if the data associated with the received tag address is contained in the cache memory may be made the control circuit, and the control circuit may update and store state information in the dual-port memory responsive to the determination.

Abstract translation: 公开了一种用于处理计算系统中的缓存请求的装置。 该装置可以包括单端口存储器，双端口存储器和控制电路。 单端口存储器可以是与高速缓冲存储器相关联的存储标签信息，并且双端口存储器可以被配置为存储与高速缓冲存储器相关联的状态信息。 控制电路可以被配置为根据接收的标签地址分别接收包括标签地址，访问标签和分别存储在单端口存储器中的状态信息和双端口存储器的请求。 可以确定与接收的标签地址相关联的数据是否包含在高速缓存存储器中，并且控制电路可以响应于该确定来更新和存储双端口存储器中的状态信息。

公开(公告)号：US08904073B2

公开(公告)日：2014-12-02

申请号：US13803769

申请日：2013-03-14

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar

IPC: G06F3/00 ,  G06F13/00 ,  G06F12/08 ,  G06F9/44 ,  G06F13/10

CPC classification number: G06F12/0815 ,  G06F3/00 ,  G06F9/4411 ,  G06F11/073 ,  G06F11/0751 ,  G06F13/102

Abstract: An apparatus for processing and tracking the progress of coherency transactions in a computing system is disclosed. The apparatus may include a finite-element state machine, a processor, and a scoreboard circuit. The finite-element state machine may be configured to track the progress of a transaction as well as detect errors during the processing of the transaction. The processor may be configured to transmit coherence requests dependent upon the transaction. The scoreboard circuit may be configured to track the requests and associate responses.

Abstract translation: 公开了一种用于处理和跟踪计算系统中的一致性事务的进展的装置。 该装置可以包括有限元状态机，处理器和记分板电路。 有限元状态机可以被配置为跟踪事务的进程以及在事务处理期间检测错误。 处理器可以被配置为发送依赖于该事务的一致性请求。 记分板电路可以被配置为跟踪请求并关联响应。

公开(公告)号：US20140189411A1

公开(公告)日：2014-07-03

申请号：US13733775

申请日：2013-01-03

Applicant: APPLE INC.

Inventor： Muditha Kanchana ,  Gurjeet S. Saund ,  Harshavardhan Kaushikkar ,  Erik P. Machnicki ,  Seye Ewedemi

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C5/144 ,  Y02D10/14

Abstract: Techniques are disclosed relating to reducing power consumption in integrated circuits. In one embodiment, an apparatus includes a cache having a set of tag structures and a power management unit. The power management unit is configured to power down a duplicate set of tag structures in responsive to the cache being powered down. In one embodiment, the cache is configured to provide, to the power management unit, an indication of whether the cache includes valid data. In such an embodiment, the power management unit is configured to power down the cache in response to the cache indicating that the cache does not include valid data. In some embodiments, the duplicate set of tag structures is located within a coherence point configured to maintain coherency between the cache and a memory.

Abstract translation: 公开了关于降低集成电路中的功耗的技术。 在一个实施例中，一种装置包括具有一组标签结构的缓存和电源管理单元。 功率管理单元被配置为响应于被断电的高速缓存而将重复的一组标签结构断电。 在一个实施例中，高速缓存被配置为向电力管理单元提供高速缓存是否包括有效数据的指示。 在这样的实施例中，功率管理单元被配置为响应于缓存指示高速缓存不包括有效数据的高速缓存来关闭高速缓存。 在一些实施例中，重复的标签结构集合位于被配置为保持高速缓存和存储器之间的一致性的相干点内。