公开(公告)号：US08464131B2

公开(公告)日：2013-06-11

申请号：US12645499

申请日：2009-12-23

申请人： Eran Sharon ,  Idan Alrod ,  Simon Litsyn

发明人： Eran Sharon ,  Idan Alrod ,  Simon Litsyn

IPC分类号： G06F11/00

CPC分类号： G11C16/26 ,  G06F11/1068 ,  G11C11/5642 ,  G11C29/00

摘要： To read memory cells that have been programmed to store an ECC codeword, with each cell storing a respective plurality of bits of the codeword, a respective value of an operational parameter such as a threshold voltage of each cell is measured. Each bit is assigned a respective metric, such as a LLR estimate of the bit, based at least in part on the respective value of the operational parameter of the bit's cell. The metrics are decoded with reference both to the ECC and to mutual constraints of the metrics within each cell that are independent of the ECC.

摘要翻译： 为了读取已编程为存储ECC码字的存储器单元，其中每个单元存储码字的相应多个位，测量诸如每个单元的阈值电压的操作参数的相应值。 至少部分地基于比特的小区的操作参数的相应值，为比特分配各个度量，例如比特的LLR估计。 参考ECC和与独立于ECC的每个单元内的度量的相互约束来对度量进行解码。

公开(公告)号：US08464123B2

公开(公告)日：2013-06-11

申请号：US12774746

申请日：2010-05-06

申请人： Idan Alrod ,  Eran Sharon ,  Simon Litsyn

发明人： Idan Alrod ,  Eran Sharon ,  Simon Litsyn

IPC分类号： H03M13/00

CPC分类号： H03M13/616 ,  G06F11/1068 ,  H03M13/1174 ,  H03M13/118 ,  H03M13/618

摘要： A plurality of information bits are encoded using a parity-check matrix that is equivalent to a modular code matrix. The modular code matrix is a diagonal sub-matrix structure immediately above a connection layer that includes a plurality of diverse connection layer sub-matrices, all but at most one of which are below corresponding diagonal matrix structure sub-matrices. The information bits are assembled with a plurality of parity bits produced by the encoding to provide a codeword that is exported to a medium. Preferably, all the diagonal matrix structure sub-matrices are identical. Preferably, some of the parity bits are computed using only diagonal matrix structure sub-matrices.

摘要翻译： 使用等同于模块代码矩阵的奇偶校验矩阵对多个信息位进行编码。 模块代码矩阵是紧邻连接层上方的对角子矩阵结构，其包括多个不同的连接层子矩阵，除了其中最多一个在相应的对角矩阵结构子矩阵之下。 信息比特与通过编码产生的多个奇偶校验位组合，以提供输出到介质的码字。 优选地，所有对角矩阵结构子矩阵是相同的。 优选地，使用仅对角矩阵结构子矩阵来计算一些奇偶校验位。

公开(公告)号：US08458563B2

公开(公告)日：2013-06-04

申请号：US12407098

申请日：2009-03-19

申请人： Eran Sharon ,  Idan Alrod ,  Simon Litsyn

发明人： Eran Sharon ,  Idan Alrod ,  Simon Litsyn

IPC分类号： G06F11/00

CPC分类号： G11C16/26 ,  G06F11/1068 ,  G11C11/5642

摘要： To read a plurality of memory cells, each cell is assigned to a respective cell population. A respective value of an operational parameter of each cell is measured. Each cell is assigned an a-priori metric based at least in part on one or more CVD parameter values of the cell's population. The a-priori metrics are decoded. Based at least in part on the resulting a-posteriori metrics, the CVD parameter values are corrected, without repeating the measurements of the cell operational parameter values. The operational parameter values are indicative of bit patterns stored in the cells, and the correction of the CVD parameter values is constrained by requiring the bit patterns collectively to be a valid codeword.

摘要翻译： 为了读取多个存储单元，将每个单元分配给相应的单元群。 测量每个单元的操作参数的相应值。 至少部分地基于单元格群体的一个或多个CVD参数值，为每个单元分配先验度量。 先验先验度量被解码。 至少部分地基于得到的后验度量，校正CVD参数值，而不重复单元操作参数值的测量。 操作参数值表示存储在单元中的位模式，并且通过要求位图集合成为有效代码字来限制CVD参数值的校正。

公开(公告)号：US08375272B2

公开(公告)日：2013-02-12

申请号：US13170193

申请日：2011-06-28

申请人： Simon Litsyn ,  Eran Sharon ,  Idan Alrod ,  Menahem Lasser

发明人： Simon Litsyn ,  Eran Sharon ,  Idan Alrod ,  Menahem Lasser

IPC分类号： H03M13/00

CPC分类号： H03M13/2927 ,  G06F11/1068 ,  H03M13/1111 ,  H03M13/152 ,  H03M13/1545 ,  H03M13/2903 ,  H03M13/2906 ,  H03M13/3715 ,  H03M13/6362

摘要： Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.

摘要翻译： 要编码的数据位被分割成多个子组。 每个子组被分别编码以产生相应的码字。 所选择的子集从相应的码字中移除，留下缩短的码字，并且被多对一地转换成浓缩比特。 最终码字是缩短的码字和浓缩比特的组合。 最终码字的表示被分割成选定的子集和多个剩余子集。 每个剩余子集被单独解码。 如果解码失败之一，则解码失败的剩余子集至少部分地根据所选子集进行解码。 如果编码和解码是系统的，则所选择的子集是奇偶校验位。

公开(公告)号：US20130031429A1

公开(公告)日：2013-01-31

申请号：US13193148

申请日：2011-07-28

申请人： Eran Sharon ,  Idan Alrod

发明人： Eran Sharon ,  Idan Alrod

IPC分类号： G06F12/00 ,  G11C29/00

CPC分类号： G11C29/04 ,  G06F11/1048 ,  G06F11/1072 ,  G11C29/82

摘要： The recovery of data during programming, such as in the case of a broken word-line, is considered. The arrangement described assumes that k pages may be corrupted when the system finishes programming a block. Then these corrupted pages can be recovered using an erasure code. In order to recover any k pages, the system will compute and temporarily store k parity pages in the controller. These k parity pages may be computed on-the-fly as the data pages are received from the host. Once programming of the block is finished, a post-write read may be done in order to validate that the data is stored reliably. If no problem is detected during EPWR, then the parity pages in the controller may be discarded. In case a problem is detected, and data in up to k pages is corrupt on some bad word-lines, then the missing data is recovered using the k parity pages that are stored in the controller and using the other non-corrupted pages that are read from the block of the memory array and decoded. Once the recovery is complete the block can be reprogrammed and the temporary parity pages in the controller may be discarded upon successfully reprogramming.

摘要翻译： 考虑在编程期间恢复数据，例如在字线断开的情况下。 所描述的布置假设当系统完成对块的编程时，k页可能被破坏。 然后可以使用擦除代码恢复这些损坏的页面。 为了恢复任何k页，系统将在控制器中计算和临时存储k个奇偶校验页面。 当从主机接收到数据页时，这些k个奇偶校验页可以在运行中计算。 一旦块的编程完成，可以进行写入后读取，以便验证数据是否被可靠地存储。 如果在EPWR期间没有检测到问题，则可能会丢弃控制器中的奇偶校验页。 如果检测到问题，并且在一些不良字线上，最多k页的数据已损坏，则使用存储在控制器中的k个奇偶校验页和使用其他未损坏的页面来恢复丢失的数据 从存储器阵列中读取并解码。 恢复完成后，可以重新编程块，并且在成功重新编程后，可能会丢弃控制器中的临时奇偶校验页。

公开(公告)号：US20130024745A1

公开(公告)日：2013-01-24

申请号：US13609984

申请日：2012-09-11

申请人： Eran Sharon ,  Simon Litsyn ,  Idan Alrod

发明人： Eran Sharon ,  Simon Litsyn ,  Idan Alrod

IPC分类号： H03M13/05

CPC分类号： H03M13/114 ,  H03M13/6505

摘要： To decode a representation of a codeword that encodes K information bits as N>K codeword bits, messages are exchanged between N bit nodes and N−K check nodes of a graph in which E edges connect the bit nodes and the check nodes. While messages are exchanged, fewer than E of the messages are stored, and/or fewer than N soft estimates of the codeword bits are stored. In some embodiments, the messages are exchanged only within sub-graphs and between the sub-graphs and one or more external check nodes. While messages are exchanged, the largest number of stored messages is the number of edges in the sub-graph with the most edges plus the number of edges that connect the sub-graphs to the external check node(s), and/or the largest number of stored soft estimates is the number of bit nodes in the sub-graph with the most bit nodes.

摘要翻译： 为了将编码K个信息比特的码字的表示解码为N个K个码字比特，消息在其中E个边缘连接比特节点和校验节点的图的N个比特节点和N-K个校验节点之间进行交换。 当消息被交换时，存储少于E个消息，和/或存储少于N个码字比特的软估计。 在一些实施例中，消息仅在子图中以及子图和一个或多个外部校验节点之间交换。 当消息被交换时，最大数量的存储消息是具有最多边缘的子图中的边数加上将子图连接到外部校验节点的边数，和/或最大 存储的软估计数是具有最多位节点的子图中的比特节点的数量。

公开(公告)号：US08315091B2

公开(公告)日：2012-11-20

申请号：US13152001

申请日：2011-06-02

申请人： Eran Sharon ,  Idan Alrod

发明人： Eran Sharon ,  Idan Alrod

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C29/16 ,  G11C16/04 ,  G11C29/50

摘要： A storage device includes a plurality of memory elements and a controller. The controller is configured to receive measured characteristics of the memory elements. The measured characteristics correspond to a plurality of values including a first value stored at a first memory element of the plurality of memory elements and a second value stored at a second memory element of the plurality of memory elements. The controller is configured to test whether at least some of the plurality of values match a particular pattern correlated to a disturb condition at the first memory element. The controller is configured to provide a data value corresponding to the first memory element, where the data value is determined at least in part based on a result of the test.

摘要翻译： 存储装置包括多个存储元件和控制器。 控制器被配置为接收存储元件的测量特性。 所测量的特性对应于多个值，包括存储在多个存储元件中的第一存储元件上的第一值和存储在多个存储元件中的第二存储元件上的第二值。 控制器被配置为测试多个值中的至少一些值是否匹配与第一存储器元件处的干扰条件相关的特定模式。 控制器被配置为提供对应于第一存储器元件的数据值，其中基于测试的结果至少部分地确定数据值。

公开(公告)号：US08085590B2

公开(公告)日：2011-12-27

申请号：US12906095

申请日：2010-10-17

申请人： Simon Litsyn ,  Eran Sharon ,  Idan Alrod

发明人： Simon Litsyn ,  Eran Sharon ,  Idan Alrod

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G06F11/1072 ,  G11C7/1006 ,  G11C11/56 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/34 ,  G11C29/42 ,  G11C2211/5641

摘要： To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits.

摘要翻译： 为了存储多个输入位，这些位被映射到一个或多个存储器单元的相应的编程状态，并且单元被编程为相应的编程状态。 映射可以是多对一的或者可以是“到”广义灰色映射。 读取单元以提供被转换成多个输出位的读取状态值，例如通过最大似然解码或通过将读取状态值映射到多个软比特中，然后解码软比特 。

公开(公告)号：US20110182118A1

公开(公告)日：2011-07-28

申请号：US13031221

申请日：2011-02-20

申请人： Simon Litsyn ,  Idan Alrod ,  Eran Sharon

发明人： Simon Litsyn ,  Idan Alrod ,  Eran Sharon

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

摘要： Each of a plurality of flash memory cells is programmed to a respective one of L≧2 threshold voltage states within a threshold voltage window. Values of parameters of threshold voltage functions are adjusted in accordance with comparisons of the threshold voltages of some or all of the cells to two or more of m≧2 threshold voltage intervals within the threshold voltage window. Reference voltages for reading the cells are selected based on the values. Alternatively, the m threshold voltage intervals span the threshold voltage window, and respective threshold voltage states are assigned to the cells based on numbers of cells whose threshold voltages are in the intervals, without re-reading the cells.

摘要翻译： 多个闪存单元中的每一个被编程为阈值电压窗口内的L≥2个阈值电压状态中的相应一个。 根据阈值电压窗口内的一些或所有单元的阈值电压与两个或多个m≥2个阈值电压间隔的比较，来调整阈值电压函数的参数值。 基于这些值来选择用于读取单元的参考电压。 或者，m阈值电压间隔跨越阈值电压窗口，并且基于阈值电压处于间隔中的单元的数量而将各个阈值电压状态分配给单元，而不重新读取单元。

公开(公告)号：US07984360B2

公开(公告)日：2011-07-19

申请号：US11876789

申请日：2007-10-23

申请人： Eran Sharon ,  Simon Litsyn ,  Idan Alrod

发明人： Eran Sharon ,  Simon Litsyn ,  Idan Alrod

IPC分类号： G11C29/00

CPC分类号： G11C11/5628 ,  G06F11/1072 ,  G11C7/1006 ,  G11C29/00

摘要： To store an input string of M N-tuples of bits, a substitution transformation is selected in accordance with the input string and is applied to the input string to provide a transformed string of M N-tuples of bits. M or more memory cells are programmed to represent the transformed string and preferably also to represent a key of the transformation. Alternatively, the memory selectively programs each of M or more cells to a respective one of 2N states. A mapping that maps the binary numbers in [0,2N−1] into respective states is selected in accordance with the input string and is used to program M cells to represent the input string. Preferably, a key of the mapping is stored in the memory in association with the M cells.

摘要翻译： 为了存储M个N元组的输入串，根据输入字符串选择替换变换，并将其应用于输入字符串，以提供M个N元组的变换字符串。 M个或更多个存储器单元被编程以表示变换的字符串，并且优选地也表示转换的关键字。 或者，存储器选择性地将M个或更多个单元中的每一个编程为2N个状态中的相应一个。 根据输入字符串选择将[0,2N-1]中的二进制数映射到各自状态的映射，并用于对M个单元进行编程以表示输入字符串。 优选地，映射的密钥与M个单元相关联地存储在存储器中。