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78 条记录 (耗时 0.022 秒)

    Control of wafer warpage during backend processing
    72.
    发明授权
    Control of wafer warpage during backend processing 有权
    后端处理期间晶圆翘曲的控制

    公开(公告)号：US07247556B2

    公开(公告)日：2007-07-24

    申请号：US11068237

    申请日：2005-02-28

    申请人： Arun K. Nanda ,  Nace Rossi

    发明人： Arun K. Nanda ,  Nace Rossi

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating an integrated circuit (IC), during which wafer warpage is controlled by appropriately controlling intrinsic stresses in one or more service layers of the layer stack of the IC's multilevel interconnect structure. In one embodiment, each interconnect level of the multilevel interconnect structure has a dielectric layer, a conducting layer formed over the dielectric layer, and a service anti-reflective coating (ARC) layer formed over the conducting layer. Each ARC layer is formed from silicon oxynitride such that at least two ARC layers corresponding to different interconnect levels have different intrinsic stresses. The amount of intrinsic stress in each ARC layer is controlled, e.g., through the control of temperature and/or gas composition during the layer deposition.

    摘要翻译： 一种制造集成电路（IC）的方法，其中通过适当地控制IC多层互连结构的层堆叠的一个或多个服务层中的固有应力来控制晶片翘曲。 在一个实施例中，多层互连结构的每个互连级别具有电介质层，形成在电介质层上的导电层，以及形成在导电层上的功能抗反射涂层（ARC）层。 每个ARC层由氮氧化硅形成，使得对应于不同互连级别的至少两个ARC层具有不同的固有应力。 每个ARC层中的固有应力的量被控制，例如通过控制层沉积期间的温度和/或气体组成。

    Shallow trench isolation structures comprising a graded doped sacrificial silicon dioxide material and a method for forming shallow trench isolation structures
    73.
    发明授权
    Shallow trench isolation structures comprising a graded doped sacrificial silicon dioxide material and a method for forming shallow trench isolation structures 有权
    包括渐变掺杂的牺牲二氧化硅材料的浅沟槽隔离结构和用于形成浅沟槽隔离结构的方法

    公开(公告)号：US07141486B1

    公开(公告)日：2006-11-28

    申请号：US11153893

    申请日：2005-06-15

    申请人： Nace Rossi ,  Ranbir Singh ,  Arun K. Nanda

    发明人： Nace Rossi ,  Ranbir Singh ,  Arun K. Nanda

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76232

    摘要： A shallow trench isolation structure having a negative taper angle. A graded doped sacrificial layer is formed over a semiconductor substrate and etched to form a first trench therein having trench sidewalls that present a negative taper angle. The substrate is also etched to form a second trench therein overlying the first trench. Silicon dioxide fills both the first and the second trenches to form the shallow trench isolation structure, with the silicon dioxide in the first trench exhibiting a negative taper angle to avoid formation of polysilicon stringers during a gate polysilicon deposition.

    摘要翻译： 具有负锥角的浅沟槽隔离结构。 梯度掺杂牺牲层形成在半导体衬底之上，并被蚀刻以形成其中具有呈负锥度角的沟槽侧壁的第一沟槽。 衬底也被蚀刻以在其中覆盖第一沟槽上形成第二沟槽。 二氧化硅填充第一和第二沟槽两者以形成浅沟槽隔离结构，其中第一沟槽中的二氧化硅呈现负锥角，以避免在栅极多晶硅沉积期间形成多晶硅桁条。

    Two phase chemical/mechanical polishing process for tungsten layers
    74.
    发明授权
    Two phase chemical/mechanical polishing process for tungsten layers 有权
    钨层的两相化学/机械抛光工艺

    公开(公告)号：US06436829B1

    公开(公告)日：2002-08-20

    申请号：US09632445

    申请日：2000-08-04

    申请人： Nace Layadi ,  Arun K. Nanda

    发明人： Nace Layadi ,  Arun K. Nanda

    IPC分类号： H01L21302

    CPC分类号： H01L21/7684 ,  H01L21/3212

    摘要： The present invention provides a method for polishing a semiconductor substrate comprising: (a) polishing a metal layer located on a semiconductor wafer with a slurry at a first polishing rate, wherein the slurry has a predetermined concentration of an oxidizing agent therein; (b) forming a diluted slurry by diluting the polishing slurry with a diluent to substantially reduce the predetermined concentration of the oxidizing agent; and (c) polishing the metal layer at a second polishing rate less than the first polishing rate and in the presence of the diluted slurry.

    摘要翻译： 本发明提供了一种用于抛光半导体衬底的方法，包括：（a）以第一抛光速率用浆料抛光位于半导体晶片上的金属层，其中所述浆料具有预定浓度的氧化剂; （b）通过用稀释剂稀释抛光浆料形成稀释的浆料，以显着降低氧化剂的预定浓度; 和（c）以小于第一研磨速率的第二抛光速率和稀释浆料的存在下抛光金属层。

    Polishing apparatus with carrier head pivoting device
    75.
    发明授权
    Polishing apparatus with carrier head pivoting device 失效
    抛光装置带有载体头枢转装置

    公开(公告)号：US6056630A

    公开(公告)日：2000-05-02

    申请号：US81406

    申请日：1998-05-19

    申请人： Arun K. Nanda ,  Laurence D. Schultz

    发明人： Arun K. Nanda ,  Laurence D. Schultz

    IPC分类号： B24B37/30 ,  B24B47/26 ,  B24B7/22

    CPC分类号： B24B37/30 ,  B24B47/26

    摘要： The present invention provides a unique polishing apparatus, such as a chemical/mechanical polishing apparatus, that includes a pivoting apparatus having a first end coupled to a carrier head and a second end coupled to a rotatable shaft wherein the pivoting apparatus is configured to exert a pivoting force with respect to the carrier head to pivot the carrier head with respect to the rotatable shaft to more easily break the surface tension formed by the slurry during the polishing process. This system provides a polishing apparatus that can reduce the amount of semiconductor wafer breakage associated with present processes and apparatus.

    摘要翻译： 本发明提供了一种独特的抛光设备，例如化学/机械抛光设备，其包括枢转设备，该枢转设备具有联接到承载头的第一端和联接到可旋转轴的第二端，其中枢转设备被配置为施加 相对于承载头的枢转力使托架头相对于可旋转轴枢转，以更容易地在抛光过程中破坏由浆料形成的表面张力。 该系统提供了能够减少与本方法和装置相关的半导体晶片断裂量的抛光装置。

    Device and method for polishing a semiconductor substrate
    76.
    发明授权
    Device and method for polishing a semiconductor substrate 失效
    用于研磨半导体衬底的装置和方法

    公开(公告)号：US6051500A

    公开(公告)日：2000-04-18

    申请号：US80992

    申请日：1998-05-19

    申请人： Alvaro Maury ,  Arun K. Nanda ,  Omar Rodriguez

    发明人： Alvaro Maury ,  Arun K. Nanda ,  Omar Rodriguez

    IPC分类号： B24B1/04 ,  B24B37/04 ,  H01L21/304 ,  H01L21/321 ,  H01L21/768

    CPC分类号： B24B1/04 ,  B24B37/042 ,  H01L21/3212 ,  H01L21/7684

    摘要： The present invention provides a method for polishing a semiconductor substrate having a first layer of material formed on a second layer of different material. In one embodiment, the method includes placing the semiconductor substrate against a polishing surface and polishing the semiconductor substrate, producing a first vibration by polishing and removing the first layer, producing a second vibration by polishing at least a portion of the second layer, and detecting a change from the first vibration to the second vibration with a vibration sensor. The vibration that is sensed in the present invention is physical or mechanical vibration, and it is not a vibration associated with a change in temperature. The vibration sensor may be of varying types. For example, the vibration sensor may be an acoustic sensor or an ultrasonic sensor.

    摘要翻译： 本发明提供一种用于研磨具有形成在不同材料的第二层上的第一材料层的半导体衬底的方法。 在一个实施例中，该方法包括将半导体衬底放置在抛光表面上并抛光半导体衬底，通过抛光和去除第一层产生第一振动，通过抛光第二层的至少一部分产生第二振动，以及检测 用振动传感器从第一次振动到第二次振动的变化。 在本发明中感测到的振动是物理或机械振动，并且它不是与温度变化相关联的振动。 振动传感器可以是不同类型的。 例如，振动传感器可以是声传感器或超声波传感器。

    Integrated circuit fabrication method
    77.
    发明授权
    Integrated circuit fabrication method 失效
    集成电路制造方法

    公开(公告)号：US5441616A

    公开(公告)日：1995-08-15

    申请号：US171123

    申请日：1993-12-21

    申请人： Arun K. Nanda ,  Mark J. Sundahl ,  Edward J. Vajda

    发明人： Arun K. Nanda ,  Mark J. Sundahl ,  Edward J. Vajda

    IPC分类号： G03F7/11 ,  H01L21/027 ,  C23C14/34 ,  H01L21/302

    CPC分类号： H01L21/0276 ,  Y10S148/017 ,  Y10S148/158 ,  Y10S438/952

    摘要： A method for forming an anti-reflective coating useful in the fabrication of integrated circuits is discussed. Applicants have found that preheating semiconductor wafers prior to the application of amorphous silicon anti-reflective coatings tends to reduce undesirable particulates which may attach to the wafer. The process is illustratively performed in a Varian 3180 machine having four stations. Illustratively, the wafer may be preheated between 70.degree. C. and 175.degree. C. prior to and during the sputter deposition of an amorphous silicon anti-reflective coating.

    摘要翻译： 讨论了用于形成集成电路的抗反射涂层的方法。 申请人已经发现，在应用非晶硅抗反射涂层之前预热半导体晶片倾向于减少可能附着到晶片的不想要的微粒。 该过程示例性地在具有四个站的Varian 3180机器中执行。 说明性地，在非晶硅抗反射涂层的溅射沉积之前和期间，晶片可以在70℃和175℃之间预热。