公开(公告)号：US08239452B2

公开(公告)日：2012-08-07

申请号：US10836566

申请日：2004-05-01

Applicant: Kevin R. Moore ,  Peyman Oreizy ,  Sean O. Blagsvedt ,  Melissa W. Dunn ,  Arvind Kumar ,  Marcus S. H. Harvey

Inventor： Kevin R. Moore ,  Peyman Oreizy ,  Sean O. Blagsvedt ,  Melissa W. Dunn ,  Arvind Kumar ,  Marcus S. H. Harvey

IPC: G06F15/16

CPC classification number: H04L67/24 ,  H04L67/18

Abstract: A system and method is provided for publication and discovery of the presence of nearby users on a network. When the system is enabled, the presence of the local user is published on the network. Nearby users that also have a similar system enabled can discover the local user's presence on the network. Furthermore, the local user may discovery the presence of the other nearby users that are currently publishing their presence on the network.

Abstract translation: 提供了一种系统和方法用于发布和发现网络上附近用户的存在。 当系统启用时，本地用户的存在将在网络上发布。 启用了类似系统的附近用户也可以发现本地用户在网络上的存在。 此外，本地用户可以发现当前在网络上发布其存在的其他附近用户的存在。

公开(公告)号：US20120181610A1

公开(公告)日：2012-07-19

申请号：US13433815

申请日：2012-03-29

Applicant: Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

Inventor： Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

IPC: H01L27/092

CPC classification number: H01L27/1104 ,  H01L27/11 ,  H01L27/1108

Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

Abstract translation: 提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。 在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。 逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压 ，SRAM nFET和SRAM pFET。

公开(公告)号：US08171321B2

公开(公告)日：2012-05-01

申请号：US11964439

申请日：2007-12-26

Applicant: Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

Inventor： Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

IPC: G06F1/00

CPC classification number: G06F1/3287 ,  G06F1/3209 ,  Y02D10/171

Abstract: A low cost, low power consumption scalable architecture is provided to allow a computer system to be managed remotely during all system power states. In a lowest power state, power is only applied to minimum logic necessary to examine a network packet. Power is applied for a short period of time to an execution subsystem and one of a plurality of cores selected to handle processing of received service requests. After processing the received service requests, the computer system returns to the lowest power state.

Abstract translation: 提供了低成本，低功耗的可扩展架构，以允许在所有系统电源状态期间远程管理计算机系统。 在最低功率状态下，功率仅适用于检查网络分组所需的最小逻辑。 将电力短时间施加到执行子系统，并且被选择用于处理所接收的服务请求的处理的多个核心中的一个。 在处理接收到的服务请求之后，计算机系统返回到最低功率状态。

公开(公告)号：US07802083B2

公开(公告)日：2010-09-21

申请号：US11613317

申请日：2006-12-20

Applicant: Nagasubramanian Gurumoorthy ,  Michael Rhodehamel ,  Arvind Kumar

Inventor： Nagasubramanian Gurumoorthy ,  Michael Rhodehamel ,  Arvind Kumar

IPC: G06F9/445 ,  G06F15/173

CPC classification number: G06F9/505 ,  G06F8/65

Abstract: Methods, apparatuses, articles, and systems for performing an installation by a client system at a time when the client system is predicted to be below a level, are disclosed. The installation may be a software or a patch. In various embodiments, the methods, apparatus et al may include performance of the adaptive prediction, and the adaptive prediction may be performed by a learning algorithm. In other embodiments, the methods et al may also develop a model of the client system's utilization by observing and recording metrics of hardware and software utilization over time.

Abstract translation: 公开了在客户端系统被预测为低于某一水平时由用户系统执行安装的方法，装置，物品和系统。 安装可能是软件或补丁程序。 在各种实施例中，方法，装置等可以包括自适应预测的执行，并且可以通过学习算法执行自适应预测。 在其他实施例中，方法等也可以通过观察和记录硬件和软件利用率随时间推移来开发客户系统利用的模型。

公开(公告)号：US07718496B2

公开(公告)日：2010-05-18

申请号：US11927964

申请日：2007-10-30

Applicant: Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

Inventor： Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

IPC: H01L21/8234 ,  H01L21/8244

CPC classification number: H01L27/1104 ,  H01L27/11 ,  H01L27/1108

Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

Abstract translation: 提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。 在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。 逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压 ，SRAM nFET和SRAM pFET。

公开(公告)号：US20100082961A1

公开(公告)日：2010-04-01

申请号：US12286352

申请日：2008-09-30

Applicant: Naga Gurumoorthy ,  Arvind Kumar ,  Matthew J. Parker

Inventor： Naga Gurumoorthy ,  Arvind Kumar ,  Matthew J. Parker

IPC: G06F9/445 ,  G06F21/00

CPC classification number: G06F21/88 ,  G06F9/4401 ,  G06F9/44542 ,  G06F21/575 ,  G06F21/73 ,  G06F2221/2141

Abstract: In some embodiments, a processor-based system may include a processor, the processor having a processor identification, one or more electronic components coupled to the processor, at least one of the electronic components having a component identification, and a hardware security component coupled to the processor and the electronic component. The hardware security component may include a secure non-volatile memory and a controller. The controller may be configured to receive the processor identification from the processor, receive the at least one component identification from the one or more electronic components, and determine if a boot of the processor-based system is a provisioning boot of the processor-based system. If the boot is determined to be the provisioning boot, the controller may be configured to store a security code in the secure non-volatile memory, wherein the security code is based on the processor identification and the at least one component identification. Other embodiments are disclosed and claimed.

Abstract translation: 在一些实施例中，基于处理器的系统可以包括处理器，处理器具有处理器标识，耦合到处理器的一个或多个电子部件，具有部件识别的电子部件中的至少一个以及耦合到 处理器和电子元件。 硬件安全组件可以包括安全的非易失性存储器和控制器。 控制器可以被配置为从处理器接收处理器标识，从一个或多个电子部件接收至少一个组件标识，并且确定基于处理器的系统的启动是否是基于处理器的系统的供应引导 。 如果确定引导是供应启动，则控制器可以被配置为将安全代码存储在安全非易失性存储器中，其中安全代码基于处理器标识和至少一个组件标识。 公开和要求保护其他实施例。

公开(公告)号：US07417288B2

公开(公告)日：2008-08-26

申请号：US11311462

申请日：2005-12-19

Applicant: Robert H. Dennard ,  Wilfried E. Haensch ,  Arvind Kumar ,  Robert J. Miller

Inventor： Robert H. Dennard ,  Wilfried E. Haensch ,  Arvind Kumar ,  Robert J. Miller

IPC: H01L29/76

CPC classification number: H01L27/1108

Abstract: A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

Abstract translation: 一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂 提供了特定的水平，以提高不同器件区域内的FET器件的性能。 特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。 为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。 在源极/漏极区域之下具有低净掺杂的非均匀横向掺杂分布和在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制。

公开(公告)号：US07389342B2

公开(公告)日：2008-06-17

申请号：US10210199

申请日：2002-07-31

Applicant: Murali Sundar ,  Arvind Kumar ,  Alok Prakash

Inventor： Murali Sundar ,  Arvind Kumar ,  Alok Prakash

IPC: G06F15/173

CPC classification number: H04L67/16 ,  H04L29/06 ,  H04L69/329

Abstract: A service creation apparatus may include an adapter communicatively coupled to a provider module by way of a uniform interface. The adapter may also be coupled to a tool via the tool's native interface. A system may include a processor coupled to a memory including the apparatus. A method for creating a service may include selecting a plurality of features provided by a native interface of a tool, collecting the plurality of features from the native interface to form a service having a uniform interface, and providing the service to a plurality of users using the uniform interface.

Abstract translation: 服务创建装置可以包括通过统一接口通信地耦合到提供者模块的适配器。 适配器还可以经由工具的本机接口耦合到工具。 系统可以包括耦合到包括该装置的存储器的处理器。 用于创建服务的方法可以包括选择由工具的本机接口提供的多个特征，从本地接口收集多个特征以形成具有统一接口的服务，并且使用 统一界面。

公开(公告)号：US07327150B2

公开(公告)日：2008-02-05

申请号：US11248775

申请日：2005-10-11

Applicant: Arvind Kumar ,  Kambiz Munshi

Inventor： Arvind Kumar ,  Kambiz Munshi

IPC: G01R27/08 ,  G01R31/26

CPC classification number: G01R31/3004 ,  G01R27/00 ,  G01R31/2884 ,  G01R31/2896

Abstract: For one embodiment, an integrated circuit includes a node to couple one or more components to the integrated circuit to carry current through a package for the integrated circuit. The integrated circuit also includes a monitor to measure a resistance of the package based at least in part on a reference resistance of the package and a resistance of one or more components that are to carry current through the package. For another embodiment, current through one or more components that are to carry current through a package for an integrated circuit is controlled. A resistance of the package is measured based at least in part on a reference resistance of the package and a resistance of one or more components that are to carry current through the package.

Abstract translation: 对于一个实施例，集成电路包括将一个或多个组件耦合到集成电路以将电流传送通过集成电路的封装的节点。 集成电路还包括至少部分地基于封装的参考电阻和用于承载电流通过封装的一个或多个部件的电阻来测量封装的电阻的监视器。 对于另一实施例，控制通过用于集成电路的用于承载电流通过封装的一个或多个部件的电流。 封装的电阻至少部分地基于封装的参考电阻和用于承载电流通过封装的一个或多个部件的电阻来测量。

公开(公告)号：US07272644B1

公开(公告)日：2007-09-18

申请号：US09675622

申请日：2000-09-29

Applicant: Arvind Kumar

Inventor： Arvind Kumar

IPC: G06F15/173 ,  G06F15/177

CPC classification number: H04L41/12 ,  H04L41/0266

Abstract: A method and apparatus for internet based network topology discovery. Extensible Markup Language (XML) based data is used to share the discovery information of devices on a network over Internet transport. XML based search engines are used to search for the discovery information. Discovery information, such as identification, location, or capability data, for example, is stored on the devices of a network in the form of XML documents. Network topology maps may be created based on the information discovered.

Abstract translation: 一种基于互联网的网络拓扑发现的方法和装置。 基于可扩展标记语言（XML）的数据用于通过互联网传输共享网络上设备的发现信息。 基于XML的搜索引擎用于搜索发现信息。 例如，识别，位置或能力数据的发现信息以XML文档的形式存储在网络的设备上。 可以基于发现的信息创建网络拓扑图。