公开(公告)号：US20120072677A1

公开(公告)日：2012-03-22

申请号：US12883848

申请日：2010-09-16

申请人： Sukalpa Biswas ,  Hao Chen

发明人： Sukalpa Biswas ,  Hao Chen

IPC分类号： G06F12/00

CPC分类号： G06F13/18

摘要： In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.

摘要翻译： 在一个实施例中，存储器控制器包括多个端口。 每个端口可能专用于不同类型的流量。 在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。 存储器控制器可以被配置为基于QoS参数在不同端口上接收的调度操作。 在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。 在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。

公开(公告)号：US20110288137A1

公开(公告)日：2011-11-24

申请号：US13180996

申请日：2011-07-12

申请人： Hao Chen ,  Ming Liu ,  Qi Su ,  Manish Raisinghani

发明人： Hao Chen ,  Ming Liu ,  Qi Su ,  Manish Raisinghani

IPC分类号： A61K31/4245 ,  A61P25/00 ,  A61P25/16 ,  A61P3/04 ,  A61P25/24 ,  A61P25/18 ,  C07D271/04 ,  A61P25/36

CPC分类号： C07D271/04 ,  A61K31/4245

摘要： Derivatives of Sydnonimine and its analogues, which bind selectively to dopamine transporter (DAT) proteins are useful for treating and delaying the progression of disorders and illnesses that are alleviated by inhibiting dopamine reuptake.

摘要翻译： Sydnonimine及其类似物的衍生物，其选择性结合多巴胺转运蛋白（DAT）蛋白质可用于治疗和延缓通过抑制多巴胺再摄取而减轻的疾病和疾病的进展。

公开(公告)号：US20110111802A1

公开(公告)日：2011-05-12

申请号：US12812822

申请日：2009-01-15

申请人： Oliver Richter ,  Stephan Spitz ,  Hao Chen

发明人： Oliver Richter ,  Stephan Spitz ,  Hao Chen

IPC分类号： H04M1/00 ,  G06F17/00

CPC分类号： H04W4/60 ,  H04L67/02 ,  H04W88/02

摘要： The invention relates to a method on a portable data carrier (10). In said method, a web server (62) of the data carrier (10) preferably receives command information from a terminal (100) connected to the data carrier (10), the command information relating to at least one CAT command (“Card Application Toolkit” command). The at least one CAT command is then executed by a CAT interpreter (64) of the data carrier (10). The command information is embedded in an HTTP command request message of an HTTP client (110) of the terminal (100), and the web server (62) extracts the embedded command information from the HTTP command request message before relaying it to the CAT interpreter (64) of the data carrier (10) for execution of the at least one CAT command. In this manner there is enabled a flexible and resource-saving interaction between the web server (62) and the CAT interpreter (64).

摘要翻译： 本发明涉及一种便携式数据载体（10）上的方法。 在所述方法中，数据载体（10）的网络服务器（62）优选地从连接到数据载体（10）的终端（100）接收命令信息，与至少一个CAT命令相关的命令信息 工具包“命令）。 然后由数据载体（10）的CAT解释器（64）执行至少一个CAT命令。 所述命令信息被嵌入到所述终端（100）的HTTP客户端（110）的HTTP命令请求消息中，并且所述Web服务器（62）在将其传递给所述CAT解释器之前从所述HTTP命令请求消息中提取所述嵌入的命令信息 （10）的数据载体（64），用于执行所述至少一个CAT命令。 以这种方式，可以在web服务器（62）和CAT解释器（64）之间实现灵活和资源节约的交互。

公开(公告)号：US07836372B2

公开(公告)日：2010-11-16

申请号：US11760566

申请日：2007-06-08

申请人： Luka Bodrozic ,  Sukalpa Biswas ,  Hao Chen ,  Sridhar P. Subramanian ,  James B. Keller

发明人： Luka Bodrozic ,  Sukalpa Biswas ,  Hao Chen ,  Sridhar P. Subramanian ,  James B. Keller

IPC分类号： G01R31/28 ,  G11C29/00

CPC分类号： G01R31/31716

摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

摘要翻译： 在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。 存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。 存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。 所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。

公开(公告)号：US20100267785A1

公开(公告)日：2010-10-21

申请号：US12740831

申请日：2008-10-27

申请人： Qiaomei Wu ,  Huiyan Gao ,  Hao Chen ,  Qiping Yan ,  Junqing Peng ,  Gongyun Hu

发明人： Qiaomei Wu ,  Huiyan Gao ,  Hao Chen ,  Qiping Yan ,  Junqing Peng ,  Gongyun Hu

IPC分类号： A61K31/4184 ,  A61P9/12

CPC分类号： A61K31/41 ,  A61K9/1623 ,  A61K9/2018 ,  A61K9/2027 ,  A61K9/2059 ,  A61K31/4184

摘要： Candesartan cilexetil-containing granules which include a sugar alcohol and a binder and which are produced by granulation with an alcoholic granulating liquid. The granules are suitable for producing tablets in which the candesartan cilexetil is present in a form stabilized with regard to decomposition.

摘要翻译： 含有蔗糖的含Cilexetil的颗粒，其包括糖醇和粘合剂，并且通过用酒精制粒液造粒。 这些颗粒适用于生产片剂，其中坎地沙坦碳酸酯以关于分解稳定的形式存在。

公开(公告)号：US07673092B2

公开(公告)日：2010-03-02

申请号：US12112079

申请日：2008-04-30

申请人： Qian Zhao ,  Hao Chen

发明人： Qian Zhao ,  Hao Chen

IPC分类号： G06F13/00

CPC分类号： G06F13/409 ,  G06F2213/0026 ,  G06F2213/0042

摘要： The present invention discloses a PCI Express interface compatible with USB interface comprising a power supply terminal and a ground terminal, in which four data terminals include two data transmitting terminals and two data receiving terminals, characterized in that the power supply terminal and the ground terminal of said interface coincide with the corresponding terminals of USB interface specification, two of said four data terminals are guaranteed to have their positions and widths overlaid with the position of terminal D+ in USB interface specification and not with the position of terminal D− in USB interface specification, and the other two data terminals are guaranteed to have their positions and widths overlaid with the position of terminal D− in USB interface specification and not with the position of terminal D+ in USB interface specification. The PCI Express interface compatible with USB interface can provide a data transmission rate up to 3 Gb/S according to PCI Express interface specification and support to the conventional USB peripheral devices without any modification on them. It further has the advantages of small-sized outline and convenience in use.

摘要翻译： 本发明公开了一种与USB接口兼容的PCI Express接口，包括电源端子和接地端子，其中四个数据端子包括两个数据发送端子和两个数据接收端子，其特征在于，电源端子和接地端子 所述接口与USB接口规范的相应端子一致，所述四个数据终端中的两个被保证具有与USB接口规范中的终端D +的位置重叠的位置和宽度，而不是在USB接口规范中的终端D的位置 ，其他两个数据终端保证其位置和宽度与USB接口规范中终端D-的位置重叠，而不是USB接口规范中终端D +的位置。 与USB接口兼容的PCI Express接口可以根据PCI Express接口规范提供高达3 Gb / S的数据传输速率，并支持传统的USB外设，无需任何修改。 它具有使用尺寸小，使用方便的优点。

公开(公告)号：US07647569B2

公开(公告)日：2010-01-12

申请号：US11832097

申请日：2007-08-01

申请人： Hao Chen ,  Chin Le ,  Stephen M. Krazit

发明人： Hao Chen ,  Chin Le ,  Stephen M. Krazit

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： Systems and methods are disclosed for organizing layout data. A layout database is analyzed to determine a statistical distribution of cells within the layout database based on a shape complexity of each cell. Cells with a shape complexity that exceeds a complex threshold may be defined as complex cells, which are examined to find candidate shapes that may be moved to one or more child cells within the complex cell. The layout database is then stored as an output layout database with at least some of these candidate shapes moved to child cells within the complex cells. Simple cells with a shape complexity that is less than a simple threshold may have their layout shapes moved to a parent cell of that simple cell. The layout database may also be partitioned into multiple dispatchable segments, which may be distributed to multiple processing threads for performing additional processes on the database.

摘要翻译： 公开了用于组织布局数据的系统和方法。 分析布局数据库以基于每个单元的形状复杂度来确定布局数据库内的单元格的统计分布。 具有超过复杂阈值的形状复杂度的细胞可以被定义为复杂细胞，其被检查以找到可以移动到复合细胞内的一个或多个子细胞的候选形状。 然后将布局数据库存储为输出布局数据库，其中这些候选形状中的至少一些移动到复合单元内的子单元。 具有小于简单阈值的形状复杂度的简单单元格可能将其布局形状移动到该简单单元格的父单元格。 布局数据库还可以被划分成多个可分派的段，其可以被分发到多个处理线程以在数据库上执行附加的进程。

公开(公告)号：US20090325711A1

公开(公告)日：2009-12-31

申请号：US12163410

申请日：2008-06-27

申请人： Manuel Bronstein ,  Manoj Gupta ,  Ivann Alvarado ,  Colin Riley ,  Matt Van Gorder ,  Hao Chen ,  Gary Hall

发明人： Manuel Bronstein ,  Manoj Gupta ,  Ivann Alvarado ,  Colin Riley ,  Matt Van Gorder ,  Hao Chen ,  Gary Hall

IPC分类号： A63F9/24

CPC分类号： A63F13/48 ,  A63F13/10 ,  A63F13/12 ,  A63F13/795 ,  A63F13/86 ,  A63F2300/5566 ,  A63F2300/5593 ,  A63F2300/577 ,  G06Q50/34

摘要： Scheduled programmatic multiplayer game content in a console service is provided. A plurality of multiplayer game events is scheduled. Each event has a fixed start time and fixed end time. Requests from users to participate in event are received and a determination is made as to whether users electing to participate in the game are eligible to participate. If the user is eligible to participate in the game, instructions are provided to a console to allow the user to participate in the game. If the user is not eligible to participate in the game, instructions may be provided to a console to allow a user to view activity in the game.

摘要翻译： 提供了在控制台服务中的预定程序化多人游戏内容。 安排多个多人游戏事件。 每个事件具有固定的开始时间和固定的结束时间。 收到用户参加活动的请求，并确定选举参与游戏的用户是否有资格参加。 如果用户有资格参与游戏，则向控制台提供指令以允许用户参与游戏。 如果用户没有资格参与游戏，则可以向控制台提供指令以允许用户查看游戏中的活动。

公开(公告)号：US20080307286A1

公开(公告)日：2008-12-11

申请号：US11758322

申请日：2007-06-05

申请人： Brian P. Lilly ,  Robert Gries ,  Sridhar P. Subramanian ,  Sukalpa Biswas ,  Hao Chen

发明人： Brian P. Lilly ,  Robert Gries ,  Sridhar P. Subramanian ,  Sukalpa Biswas ,  Hao Chen

IPC分类号： H03M13/00

CPC分类号： H03M13/09 ,  G06F11/1004

摘要： In one embodiment, an apparatus comprises a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission comprising M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.

摘要翻译： 在一个实施例中，一种装置包括耦合到控制电路的检查/校正电路。 检查/校正电路被耦合以接收数据块和相应的校验位。 数据块作为N个传输被接收，每个传输包括M个数据位和L个校验位。 检查/校正电路被配置为响应于M个数据位和L个校验位来检测M个数据位中K位的多个非重叠窗口中的每一个中的一个或多个错误。 控制电路被配置为记录多个窗口中哪一个具有检测到的错误，并且如果多个窗口的给定窗口在块的N个传输中的每一个中都检测到错误，则控制电路被配置为发信号 设备故障 K，L，M和N中的每一个是大于1的整数。

公开(公告)号：US20080307276A1

公开(公告)日：2008-12-11

申请号：US11760566

申请日：2007-06-08

申请人： Luka Bodrozic ,  Sukalpa Biswas ,  Hao Chen ,  Sridhar P. Subramanian ,  James B. Keller

发明人： Luka Bodrozic ,  Sukalpa Biswas ,  Hao Chen ,  Sridhar P. Subramanian ,  James B. Keller

IPC分类号： G11C29/04 ,  G06F12/00

CPC分类号： G01R31/31716

摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

摘要翻译： 在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。 存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。 存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。 所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。