公开(公告)号：US06756643B1

公开(公告)日：2004-06-29

申请号：US10459579

申请日：2003-06-12

Applicant: Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L2976

CPC classification number: H01L29/785 ,  H01L21/3212 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681

Abstract: A FinFET-type semiconductor device includes a fin structure on which a relatively thin amorphous silicon layer and then an undoped polysilicon layer is formed. The semiconductor device may be planarized using a chemical mechanical polishing (CMP) in which the amorphous silicon layer acts as a stop layer to prevent damage to the fin structure.

Abstract translation: FinFET型半导体器件包括翅片结构，其上形成相对薄的非晶硅层，然后形成未掺杂的多晶硅层。 半导体器件可以使用化学机械抛光（CMP）进行平面化，其中非晶硅层用作阻挡层以防止损坏鳍结构。

公开(公告)号：US06746926B1

公开(公告)日：2004-06-08

申请号：US09844752

申请日：2001-04-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/823807 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7834

Abstract: A method for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves a highly localized halo implant formed in the channel region but not in the source/drain junction. The halo implant is performed through a gap formed by removal of a temporary spacer. The MOSFET is then further completed.

Abstract translation: 一种改进深亚微米场效应晶体管和MOSFET的沟道掺杂分布的方法。 该方法包括形成在沟道区域中而不是在源极/漏极结中的高度局部化的卤素注入。 通过移除临时间隔物形成的间隙进行晕轮植入。 然后，MOSFET进一步完成。

公开(公告)号：US06664146B1

公开(公告)日：2003-12-16

申请号：US09873170

申请日：2001-06-01

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2184

CPC classification number: H01L21/76264 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

Abstract: For fabricating field effect transistors with a semiconductor substrate in SOI (semiconductor on insulator) technology, a first hardmask is formed on a first area of the semiconductor substrate, and a first dielectric forming dopant is implanted into a second area of the semiconductor substrate that is not covered by the first hardmask. The first hardmask is removed from the first area of the semiconductor substrate. A second hardmask is formed on the second area of the semiconductor substrate, and a second dielectric forming dopant is implanted into the first area of the semiconductor substrate that is not covered by the second hardmask. A thermal anneal is performed to form a first buried insulating structure from the second dielectric forming dopant reacting within the first area of the semiconductor substrate and to form a second buried insulating structure from the first dielectric forming dopant reacting within the second area of the semiconductor substrate. A first semiconductor structure remains on top of the first buried insulating structure and has a different thickness from a second semiconductor structure remaining on top of the second buried insulating structure.

Abstract translation: 为了在SOI（绝缘体上半导体）技术中制造具有半导体衬底的场效应晶体管，在半导体衬底的第一区域上形成第一硬掩模，并且将第一电介质形成掺杂剂注入到半导体衬底的第二区域 没有被第一个硬掩模覆盖。 第一硬掩模从半导体衬底的第一区域去除。 第二硬掩模形成在半导体衬底的第二区域上，并且第二电介质形成掺杂剂注入到半导体衬底的未被第二硬掩模覆盖的第一区域中。 进行热退火，以形成第一掩埋绝缘结构，从第二电介质形成掺杂剂在半导体衬底的第一区域内反应，并形成第二掩埋绝缘结构，从第一电介质形成掺杂剂在半导体衬底的第二区域内反应 。 第一半导体结构保留在第一掩埋绝缘结构的顶部，并且具有与保留在第二掩埋绝缘结构的顶部上的第二半导体结构不同的厚度。

公开(公告)号：US06645797B1

公开(公告)日：2003-11-11

申请号：US10310926

申请日：2002-12-06

Applicant: Matthew S. Buynoski ,  Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Haihong Wang ,  Chih-Yuh Yang ,  Bin Yu

Inventor： Matthew S. Buynoski ,  Srikanteswara Dakshina-Murthy ,  Cyrus E. Tabery ,  Haihong Wang ,  Chih-Yuh Yang ,  Bin Yu

IPC: H01L2184

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mask over the carbon layer. The method further includes etching the mask and carbon layer to form at least one structure, where the structure has a first width, reducing the width of the carbon layer in the at least one structure to a second width, depositing an oxide layer to surround the at least one structure, removing a portion of the oxide layer and the mask, removing the carbon layer to form an opening in a remaining portion of the oxide layer for each of the at least one structure, filling the at least one opening with conductive material, and removing the remaining portion of the oxide layer and a portion of the conductive layer to form the fin.

Abstract translation: 一种在半导体器件中形成翅片的方法，包括：衬底，形成在衬底上的绝缘层和形成在绝缘层上的导电层，包括在导电层上形成碳层，并在碳层上形成掩模 。 该方法还包括蚀刻掩模和碳层以形成至少一种结构，其中结构具有第一宽度，将至少一个结构中的碳层的宽度减小到第二宽度，沉积氧化物层以围绕 至少一个结构，去除所述氧化物层和所述掩模的一部分，除去所述碳层以在所述至少一个结构中的每一个结构的氧化物层的剩余部分中形成开口，用导电材料填充所述至少一个开口 并且去除氧化物层的剩余部分和导电层的一部分以形成翅片。

公开(公告)号：US06555437B1

公开(公告)日：2003-04-29

申请号：US09844888

申请日：2001-04-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628

Abstract: A method and device for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves forming a multi-graded lateral channel doping profile by dual halo implants annealed at different temperatures to improve the threshold voltage roll-off characteristics of MOSFETs of 50 nm or less. The method includes forming a spacer on the sidewalls of a gate, followed by forming source/drain regions by epitaxial growth followed by a deep source/drain implant and anneal. After removal of the spacer, the first angled deep halo implant through the space formed by removal of the spacer and a second annealing at a temperature lower than the first anneal occurs. A second angled halo implant and a third anneal at a temperature less than the second anneal is performed. The microelectronic chip is then silicided and the MOSFET is further completed.

Abstract translation: 一种用于改善深亚微米场效应晶体管和MOSFET的沟道掺杂分布的方法和装置。 该方法包括通过在不同温度下退火的双光晕植入物形成多梯度横向沟道掺杂分布，以改善50nm或更小的MOSFET的阈值电压滚降特性。 该方法包括在栅极的侧壁上形成间隔物，随后通过外延生长随后进行深源极/漏极注入和退火来形成源极/漏极区域。 在去除间隔物之后，通过去除间隔物形成的空间的第一倾斜的深晕注入和在低于第一退火的温度下进行第二次退火。 执行第二倾斜的晕轮植入物和在小于第二退火的温度下的第三退火。 然后将微电子芯片硅化并且MOSFET进一步完成。

公开(公告)号：US06521502B1

公开(公告)日：2003-02-18

申请号：US09633207

申请日：2000-08-07

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2100

CPC classification number: H01L29/6659 ,  H01L21/2022 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1083

Abstract: A method of manufacturing an integrated circuit may include the steps of forming a deep amorphous region and doping the deep amorphous region. The doping of the deep amorphous region can form source and drain regions with extensions. After doping, the substrate is annealed. The annealing can occur at a low temperature.

Abstract translation: 制造集成电路的方法可以包括形成深非晶区域并掺杂深非晶区域的步骤。 深非晶区域的掺杂可以形成具有延伸的源极和漏极区域。 掺杂后，将基板退火。 退火可以在低温下进行。

公开(公告)号：US06514829B1

公开(公告)日：2003-02-04

申请号：US09803831

申请日：2001-03-12

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66772 ,  H01L21/26586 ,  H01L29/458 ,  H01L29/78684

Abstract: A method of fabricating an integrated circuit forming abrupt source/drain junctions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs) on a silicon-on-insulator (SOI) substrate. The source extension is more conductive than the drain extension. The transistor has reduced short channel effects and strong drive current and yet is reliable.

Abstract translation: 一种形成突发的源极/漏极结的集成电路的方法。 该工艺可用于绝缘体上硅（SOI）衬底上的P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。 源极延伸比漏极延伸更为导电。 晶体管减少了短沟道效应和强大的驱动电流，而且可靠。

公开(公告)号：US06506650B1

公开(公告)日：2003-01-14

申请号：US09843782

申请日：2001-04-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66598 ,  H01L21/26506 ,  H01L21/2652 ,  H01L29/6656 ,  H01L29/6659

Abstract: A MOSFET transistor and method of fabrication are described for engineering the channel dopant profile within a MOSFET transistor utilizing a single deep implantation step and solid-phase epitaxy. The method utilizes the formation of an L-shaped spacer having reduced height “cutouts” adjacent to the gate stack. The L-shaped spacer is preferably created by depositing two layers of insulating material, over which a third spacer is formed as a mask for removing unwanted portions of the first and second insulation layers. Amorphization and deep implantation is performed through the L-shaped spacer, wherein the junction contour is profiled in response to the geometry of the L-shaped spacer, such that a single deep implantation step may be utilized. Pocketed steps within the contoured junction reduce short-channel effects while allowing the formation of silicide to a depth which exceeds the junction depth implanted beneath the gate electrode.

Abstract translation: 描述了一种MOSFET晶体管及其制造方法，用于通过单个深度注入步骤和固相外延来在MOSFET晶体管内工程化沟道掺杂物分布。 该方法利用形成邻近栅极叠层的具有减小的高度“切口”的L形间隔物。 优选地，通过沉积两层绝缘材料来形成L形间隔件，在其上形成第三间隔件作为掩模，以去除第一和第二绝缘层的不期望的部分。 通过L形间隔件执行非晶化和深度注入，其中响应于L形间隔件的几何形状，连接轮廓被成型，使得可以利用单个深度注入步骤。 轮廓结中的凹槽可以减少短沟道效应，同时允许硅化物的形成深度超过浇注在栅电极下方的结深度。

公开(公告)号：US06506638B1

公开(公告)日：2003-01-14

申请号：US09689063

申请日：2000-10-12

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2100

CPC classification number: H01L29/66666 ,  H01L29/7827

Abstract: A method of manufacturing a vertical transistor. The vertical transistor utilizes a deposited amorphous silicon layer to form a source region. The vertical gate transistor includes a double gate structure for providing increased drive current. A wafer bonding technique can be utilized to form the substrate.

Abstract translation: 一种垂直晶体管的制造方法。 垂直晶体管利用沉积的非晶硅层形成源区。 垂直栅极晶体管包括用于提供增加的驱动电流的双栅极结构。 可以利用晶片接合技术来形成衬底。

公开(公告)号：US06495402B1

公开(公告)日：2002-12-17

申请号：US09777637

申请日：2001-02-06

Applicant: Bin Yu ,  Ralf van Bentum

Inventor： Bin Yu ,  Ralf van Bentum

IPC: H01L2100

CPC classification number: H01L29/66477 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78684

Abstract: A semiconductor-on-insulator (SOI) device. The SOI device includes a substrate having a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer, the active layer having an active region defined by isolation regions, the active region having a source and a drain with a body disposed therebetween, each of the source and the drain having a selectively grown silicon-germanium region disposed under an upper layer of selectively grown silicon, the silicon-germanium regions forming heterojunction portions respectively along the source/body junction and the drain/body junction. A method of fabricating the SOI device is also disclosed.

Abstract translation: 绝缘体上半导体（SOI）器件。 SOI器件包括其上设置有掩埋氧化物层的衬底和设置在掩埋氧化物层上的有源层，该有源层具有由隔离区域限定的有源区域，该有源区域具有源极和漏极，其间设置有一个主体 源极和漏极中的每一个具有选择性地生长的硅 - 锗区域，其设置在选择性生长的硅的上层之下，硅 - 锗区域分别沿着源极/主体结和漏极/本体结形成异质结部分。 还公开了制造SOI器件的方法。