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78 条记录 (耗时 0.026 秒)

    Semiconductor devices and methods of fabricating the same
    71.
    发明申请
    Semiconductor devices and methods of fabricating the same 有权
    半导体器件及其制造方法

    公开(公告)号：US20070122979A1

    公开(公告)日：2007-05-31

    申请号：US11604943

    申请日：2006-11-28

    申请人： Chang-Woo Oh ,  Ki-Whan Song

    发明人： Chang-Woo Oh ,  Ki-Whan Song

    IPC分类号： H01L21/336 ,  H01L29/76

    CPC分类号： H01L27/1203 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/785

    摘要： Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a second gate line formed in the pattern of spacer on the second sidewall of the fin. First and second impurity regions are disposed in the fin. The first and second impurity regions are isolated from each other and define a channel region in the fin between the first and second gate lines.

    摘要翻译： 公开了半导体器件及其制造方法。 该器件设置在基板上，包括由第一和第二侧壁构成的鳍片，在鳍片的第一侧壁上以间隔物图案形成的第一栅极线和形成在第二栅极上的间隔物图案中的第二栅极线 鳍的侧壁 第一和第二杂质区域设置在翅片中。 第一和第二杂质区彼此隔离并且在第一和第二栅极线之间的鳍中限定沟道区。

    Methods of forming fin field effect transistors using oxidation barrier layers and related devices
    74.
    发明申请
    Methods of forming fin field effect transistors using oxidation barrier layers and related devices 有权
    使用氧化阻挡层和相关器件形成鳍式场效应晶体管的方法

    公开(公告)号：US20050272192A1

    公开(公告)日：2005-12-08

    申请号：US11020899

    申请日：2004-12-23

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Yong-Kyu Lee

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/786

    CPC分类号： H01L29/7854 ,  B82Y10/00 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/78645

    摘要： A method of forming a fin field effect transistor on a semiconductor substrate includes forming a fin-shaped active region vertically protruding from the substrate. An oxide layer is formed on a top surface and opposing sidewalls of the fin-shaped active region. An oxidation barrier layer is formed on the opposing sidewalls of the fin-shaped active region and is planarized to a height no greater than about a height of the oxide layer to form a fin structure. The fin structure is oxidized to form a capping oxide layer on the top surface of the fin-shaped active region and to form at least one curved sidewall portion proximate the top surface of the fin-shaped active region. The oxidation barrier layer has a height sufficient to reduce oxidation on the sidewalls of the fin-shaped active region about halfway between the top surface and a base of the fin-shaped active region. Related devices are also discussed.

    摘要翻译： 在半导体衬底上形成鳍状场效应晶体管的方法包括形成从衬底垂直突出的鳍状有源区。 在鳍状有源区的上表面和相对侧壁上形成氧化物层。 在翅片状有源区域的相对的侧壁上形成氧化阻挡层，并将其平坦化至不大于氧化物层高度的高度以形成翅片结构。 翅片结构被氧化以在翅片形有源区的顶表面上形成封盖氧化层，并且在翅片形有源区的顶表面附近形成至少一个弯曲的侧壁部分。 氧化阻挡层的高度足以减小翅片形有源区的侧壁上的氧化，大约在鳍状有源区的顶表面和基底之间的一半处。 还讨论了相关设备。

    Surrounded-channel transistors with directionally etched gate or insulator formation regions and methods of fabrication therefor
    76.
    发明申请
    Surrounded-channel transistors with directionally etched gate or insulator formation regions and methods of fabrication therefor 有权
    具有定向蚀刻的栅极或绝缘体形成区域的周围通道晶体管及其制造方法

    公开(公告)号：US20050224889A1

    公开(公告)日：2005-10-13

    申请号：US11095969

    申请日：2005-03-31

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Sung-Young Lee

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Sung-Young Lee

    IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/76 ,  H01L29/786

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78645 ,  Y10S438/924

    摘要： An elongate stacked semiconductor structure is formed on a substrate. The stacked semiconductor structure includes a second semiconductor material region disposed on a first semiconductor material region. The first semiconductor material region is selectively doped to produce spaced-apart impurity-doped first semiconductor material regions and a lower dopant concentration first semiconductor material region therebetween. Etching exposes a portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. The etching removes at least a portion of the lower dopant concentration first semiconductor material region to form a hollow between the substrate and the portion of the second semiconductor material region between the impurity-doped first semiconductor material regions. An insulation layer that surrounds the exposed portion of the second semiconductor material region between the impurity-doped first semiconductor material regions is formed. The hollow may be filled with a gate electrode that completely surrounds the exposed portion of the second semiconductor material region, or the gate electrode may partially surround the exposed portion of the second semiconductor material region and an insulation region may be formed in the hollow.

    摘要翻译： 在衬底上形成细长的堆叠半导体结构。 层叠的半导体结构包括设置在第一半导体材料区域上的第二半导体材料区域。 第一半导体材料区域被选择性地掺杂以产生间隔杂质掺杂的第一半导体材料区域和其间的较低掺杂浓度的第一半导体材料区域。 蚀刻使杂质掺杂的第一半导体材料区域之间的第二半导体材料区域的一部分暴露。 蚀刻去除下掺杂剂浓度的第一半导体材料区域的至少一部分，以在衬底与掺杂杂质的第一半导体材料区域之间的第二半导体材料区域的部分之间形成中空。 形成了在杂质掺杂的第一半导体材料区域之间围绕第二半导体材料区域的暴露部分的绝缘层。 中空部可以填充有完全围绕第二半导体材料区域的暴露部分的栅电极，或者栅电极可以部分地围绕第二半导体材料区域的暴露部分，并且可以在中空部中形成绝缘区域。

    Semiconductor device employing buried insulating layer and method of fabricating the same
    77.
    发明申请
    Semiconductor device employing buried insulating layer and method of fabricating the same 有权
    采用埋层绝缘层的半导体器件及其制造方法

    公开(公告)号：US20050133881A1

    公开(公告)日：2005-06-23

    申请号：US11011258

    申请日：2004-12-13

    申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Kyoung-Hwan Yeo

    发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Kyoung-Hwan Yeo

    IPC分类号： H01L27/108 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242 ,  H01L29/00 ,  H01L29/06

    CPC分类号： H01L29/66651 ,  H01L27/10873 ,  H01L29/0653 ,  H01L29/66659

    摘要： A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.

    摘要翻译： 半导体器件采用非对称埋层绝缘层及其制造方法。 半导体器件包括下半导体衬底。 上硅图案位于下半导体衬底上。 上部硅图案包括通道区域以及由沟道区域彼此间隔开的源极区域和漏极区域。 栅电极与上硅图案电绝缘，并且在沟道区域上相交。 位线和单元电容器分别电连接到源极区域和漏极区域。 掩埋绝缘层插入在漏区和下半导体衬底之间。 掩埋绝缘层具有部分插入在沟道区域和下半导体衬底之间的延伸部分。