公开(公告)号：US20050098094A1

公开(公告)日：2005-05-12

申请号：US10982554

申请日：2004-11-05

申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Mia-Sang Kim ,  Sung-Ming Kim

发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Mia-Sang Kim ,  Sung-Ming Kim

IPC分类号： H01L21/336 ,  C30B23/00 ,  H01L21/331 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L21/823481 ,  H01L21/76283 ,  H01L29/1079 ,  H01L29/78

摘要： Embodiments of the invention include a partially insulated field effect transistor and a method of fabricating the same. According to some embodiments, a semiconductor substrate is formed by sequentially stacking a bottom semiconductor layer, a sacrificial layer, and a top semiconductor layer. The sacrificial layer may be removed to form a buried gap region between the bottom semiconductor layer and the top semiconductor layer. Then, a transistor may be formed on the semiconductor substrate. The sacrificial layer may be a crystalline semiconductor formed by an epitaxial growth technology.

摘要翻译： 本发明的实施例包括部分绝缘的场效应晶体管及其制造方法。 根据一些实施例，通过顺序堆叠底部半导体层，牺牲层和顶部半导体层来形成半导体衬底。 可以去除牺牲层以在底部半导体层和顶部半导体层之间形成掩埋间隙区域。 然后，可以在半导体衬底上形成晶体管。 牺牲层可以是通过外延生长技术形成的晶体半导体。

公开(公告)号：US20100127328A1

公开(公告)日：2010-05-27

申请号：US12696125

申请日：2010-01-29

申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

IPC分类号： H01L27/12

CPC分类号： H01L29/785 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/78603

摘要： An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining.

摘要翻译： 通过在其上提供具有牺牲层的衬底，在远离衬底的牺牲层上的有源半导体层和沿着有源半导体层和牺牲层的至少两侧延伸的支撑层来制造SOI衬底 衬底，并且暴露出牺牲层的至少一侧。 牺牲层中的至少一部分被蚀刻穿过其至少一侧，其被支撑层暴露以在衬底和有源半导体层之间形成空隙，使得有源半导体层以间隔的关系支撑 通过支撑层从衬底。 空隙空间可以至少部分地填充有绝缘体衬里。

公开(公告)号：US20070257312A1

公开(公告)日：2007-11-08

申请号：US11774240

申请日：2007-07-06

申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/78603

摘要： An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining.

摘要翻译： 通过在其上提供具有牺牲层的衬底，在远离衬底的牺牲层上的有源半导体层和沿着有源半导体层和牺牲层的至少两侧延伸的支撑层来制造SOI衬底 衬底，并且暴露出牺牲层的至少一侧。 牺牲层中的至少一部分被蚀刻穿过其至少一侧，其被支撑层暴露以在衬底和有源半导体层之间形成空隙，使得有源半导体层以间隔的关系支撑 通过支撑层从衬底。 空隙空间可以至少部分地填充有绝缘体衬里。

公开(公告)号：US20070184611A1

公开(公告)日：2007-08-09

申请号：US11696132

申请日：2007-04-03

申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

IPC分类号： H01L21/8242

CPC分类号： H01L27/10802 ,  H01L27/0214 ,  H01L27/10873 ,  H01L29/7841 ,  H01L29/78612

摘要： According to some embodiments, a semiconductor device includes a lower semiconductor substrate, an upper silicon pattern, and a MOS transistor. The MOS transistor includes a body region formed within the upper silicon pattern and source/drain regions separated by the body region. A buried insulating layer is interposed between the lower semiconductor substrate and the upper silicon pattern. A through plug penetrates the buried insulating layer and electrically connects the body region with the lower semiconductor substrate, the through plug positioned closer to one of the source/drain regions than the other source/drain region. At least some portion of the upper surface of the through plug is positioned outside a depletion layer when a source voltage is applied to the one of the source/drain regions, and the upper surface of the through plug is positioned inside the depletion layer when a drain voltage is applied to the one region.

摘要翻译： 根据一些实施例，半导体器件包括下半导体衬底，上硅图案和MOS晶体管。 MOS晶体管包括形成在上硅图案内的主体区域和由身体区域分离的源极/漏极区域。 掩埋绝缘层插入在下半导体衬底和上硅图案之间。 穿通插塞穿透埋入的绝缘层并且电连接体区域与下半导体衬底，穿通插塞比另一个源极/漏极区域更靠近源极/漏极区域之一。 当源极电压施加到源极/漏极区域之一时，贯通插塞的上表面的至少一部分位于耗尽层的外侧，并且当通过插塞的上表面位于耗尽层内时， 漏极电压施加到该区域。

公开(公告)号：US20050110159A1

公开(公告)日：2005-05-26

申请号：US10977702

申请日：2004-10-28

申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

IPC分类号： H01L23/12 ,  H01L21/762 ,  H01L21/822 ,  H01L25/065 ,  H01L27/06 ,  H01L29/04

CPC分类号： H01L21/76251 ,  H01L21/8221 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a stacked integrated circuit device including multiple substrates and a method of manufacturing the same. A first integrated circuit substrate, a first integrated circuit formed on the first integrated circuit substrate, and a first passivation insulating layer are sequentially formed. Then, wafer bonding technique for forming an SOI substrate is used, thereby forming a second integrated circuit substrate on the first passivation insulating layer. While forming a second integrated circuit on the second integrated circuit substrate, at least one device-connecting interconnect electrically connects the first and second Integrated circuits and penetrates the second integrated circuit substrate and the first passivation layer. A second passivation insulating layer is formed on an upper surface of the second integrated circuit.

摘要翻译： 提供了包括多个基板的堆叠集成电路器件及其制造方法。 依次形成第一集成电路基板，形成在第一集成电路基板上的第一集成电路和第一钝化绝缘层。 然后，使用用于形成SOI衬底的晶片接合技术，从而在第一钝化绝缘层上形成第二集成电路衬底。 当在第二集成电路衬底上形成第二集成电路时，至少一个器件连接互连电连接第一和第二集成电路并且穿透第二集成电路衬底和第一钝化层。 第二钝化绝缘层形成在第二集成电路的上表面上。

公开(公告)号：US08466511B2

公开(公告)日：2013-06-18

申请号：US12613025

申请日：2009-11-05

申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Dong-Won Kim

发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe ,  Dong-Won Kim

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/78618

摘要： A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.

摘要翻译： 翅片场效应晶体管（FinFET）器件包括其中具有第一和第二源极/漏极区域的鳍状有源区域以及从半导体衬底垂直突出的沟道区域。 栅电极形成在沟道区的上表面和侧壁上。 第一和第二源极/漏极触点形成在栅极电极的相对侧的鳍状有源区域的第一和第二源极/漏极区域的相应上表面和侧壁上。 沟道区域可以比鳍状有源区域的第一和第二源极/漏极区域窄。

公开(公告)号：US07214987B2

公开(公告)日：2007-05-08

申请号：US11011911

申请日：2004-12-13

申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Jeong-Dong Choe

IPC分类号： H01L27/12 ,  H01L27/01

CPC分类号： H01L27/10802 ,  H01L27/0214 ,  H01L27/10873 ,  H01L29/7841 ,  H01L29/78612

摘要： According to some embodiments, a semiconductor device includes a lower semiconductor substrate, an upper silicon pattern, and a MOS transistor. The MOS transistor includes a body region formed within the upper silicon pattern and source/drain regions separated by the body region. A buried insulating layer is interposed between the lower semiconductor substrate and the upper silicon pattern. A through plug penetrates the buried insulating layer and electrically connects the body region with the lower semiconductor substrate, the through plug positioned closer to one of the source/drain regions than the other source/drain region. At least some portion of the upper surface of the through plug is positioned outside a depletion layer when a source voltage is applied to the one of the source/drain regions, and the upper surface of the through plug is positioned inside the depletion layer when a drain voltage is applied to the one region.

摘要翻译： 根据一些实施例，半导体器件包括下半导体衬底，上硅图案和MOS晶体管。 MOS晶体管包括形成在上硅图案内的主体区域和由身体区域分离的源极/漏极区域。 掩埋绝缘层插入在下半导体衬底和上硅图案之间。 穿通插塞穿透埋入的绝缘层并且电连接体区域与下半导体衬底，穿通插塞比另一个源极/漏极区域更靠近源极/漏极区域之一。 当源极电压施加到源极/漏极区域之一时，贯通插塞的上表面的至少一部分位于耗尽层的外侧，并且当通过插塞的上表面位于耗尽层内时， 漏极电压施加到该区域。

公开(公告)号：US20050227424A1

公开(公告)日：2005-10-13

申请号：US11090740

申请日：2005-03-24

申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Jeong-Dong Choe

发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Dong-Won Kim ,  Jeong-Dong Choe

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/786

CPC分类号： H01L29/785 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78687 ,  Y10S438/933

摘要： A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses over the device active pattern, interposed by a gate insulation layer. A support pattern is preferably interposed between the device active pattern and the substrate. The support pattern can be disposed under the gate electrode. A filling insulation pattern is preferably disposed between the device active pattern and the filling insulation pattern. The filling insulation pattern may be disposed under the source/drain region. A device active pattern under the gate electrode is preferably formed of a strained silicon having a lattice width wider than a silicon lattice.

摘要翻译： 提供具有场效应晶体管的半导体器件及其形成方法。 半导体器件优选地包括设置在衬底的预定区域上的器件有源图案。 栅电极优选地跨过器件有源图案，由栅极绝缘层插入。 支撑图案优选地插入在器件活性图案和基底之间。 支撑图案可以设置在栅电极下方。 填充绝缘图案优选地设置在装置活性图案和填充绝缘图案之间。 填充绝缘图案可以设置在源极/漏极区域下方。 栅电极下方的器件有源图案优选由具有比硅晶格宽的晶格宽度的应变硅形成。

公开(公告)号：US06951785B2

公开(公告)日：2005-10-04

申请号：US10832080

申请日：2004-04-26

申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Chang-Sub Lee

发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Jeong-Dong Choe ,  Chang-Sub Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/66621 ,  H01L29/66537 ,  H01L29/66553

摘要： A method of forming a field effect transistor may include forming a doped layer at a surface of a semiconductor substrate, and forming a groove through the doped layer at the surface of the semiconductor substrate while maintaining portions of the doped layer on opposite sides of the groove. A gate insulating layer may be formed on a surface of the groove, and a gate electrode may be formed on the gate insulating layer in the groove.

摘要翻译： 形成场效应晶体管的方法可以包括在半导体衬底的表面上形成掺杂层，并且在半导体衬底的表面上形成通过掺杂层的沟槽，同时保持掺杂层在槽的相对侧上的部分 。 可以在沟槽的表面上形成栅极绝缘层，并且可以在沟槽中的栅极绝缘层上形成栅电极。

公开(公告)号：US07883969B2

公开(公告)日：2011-02-08

申请号：US12106683

申请日：2008-04-21

申请人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Chang-Sub Lee ,  Jeong-Dong Choe

发明人： Chang-Woo Oh ,  Dong-Gun Park ,  Sung-Young Lee ,  Chang-Sub Lee ,  Jeong-Dong Choe

IPC分类号： H01L21/336

CPC分类号： H01L29/66583 ,  H01L29/1037 ,  H01L29/66651

摘要： Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.

摘要翻译： 提供金属氧化物半导体（MOS）晶体管的单位电池，其在集成电路基板上具有集成电路基板和MOS晶体管。 MOS晶体管包括源极区，漏极区和栅极。 栅极在源极区域和漏极区域之间。 在源区和漏区之间提供沟道区。 沟道区具有比源区和漏区的底表面低的凹陷区域。 还提供了制造晶体管的相关方法。