公开(公告)号：US08455363B2

公开(公告)日：2013-06-04

申请号：US13282593

申请日：2011-10-27

Applicant: Tzung-Han Lee ,  Chung-Lin Huang

Inventor： Tzung-Han Lee ,  Chung-Lin Huang

IPC: H01L21/311

CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/3083

Abstract: A method for adjusting the trench depth of a substrate has the steps as follows. Forming a patterned covering layer on the substrate, wherein the patterned covering layer defines a wider spacing and a narrower spacing. Forming a wider buffering layer arranged in the wider spacing and a narrower buffering layer arranged in the narrower spacing. The thickness of the narrower buffering layer is thinner than the wider buffering layer. Implementing dry etching process to make the substrate corresponding to the wider and the narrower buffering layers form a plurality of trenches. When etching the wider and the narrower buffering layers, the narrower buffering layer is removed firstly, so that the substrate corresponding to the narrower buffering layer will be etched early than the substrate corresponding to the wider buffering layer.

Abstract translation: 用于调整衬底的沟槽深度的方法具有以下步骤。 在衬底上形成图案化的覆盖层，其中图案化覆盖层限定更宽的间隔和更窄的间隔。 形成更宽的间隔布置的较宽的缓冲层和以较窄的间隔布置的较窄的缓冲层。 较窄的缓冲层的厚度比较宽的缓冲层薄。 实施干蚀刻工艺以使与较宽和较窄缓冲层相对应的衬底形成多个沟槽。 当蚀刻较宽和较窄的缓冲层时，首先去除较窄的缓冲层，使得对应于较窄缓冲层的衬底将比对应于较宽缓冲层的衬底早蚀刻。

公开(公告)号：US08298892B1

公开(公告)日：2012-10-30

申请号：US13241295

申请日：2011-09-23

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC: H01L21/336

CPC classification number: H01L27/105 ,  H01L21/76224 ,  H01L29/4236

Abstract: A fabricating method of an insulator for replacing a gate structure in a substrate by the insulator. The fabricating method includes the step of providing a substrate including a first buried gate structure. The first buried structure includes a first trench embedded in the substrate and a first gate filling in the first trench. The first trench has a first depth. Then, the first gate of the first buried structure is removed. Later, the substrate under the first trench is etched to elongate the depth of the first trench from the first depth to a third depth. Finally, an insulating material fills in the first trench with the third depth to form an insulator of the present invention.

Abstract translation: 一种绝缘体的制造方法，用于通过绝缘体代替衬底中的栅极结构。 制造方法包括提供包括第一掩埋栅极结构的衬底的步骤。 第一掩埋结构包括嵌入衬底中的第一沟槽和填充在第一沟槽中的第一栅极。 第一个沟槽有第一个深度。 然后，去除第一掩埋结构的第一栅极。 之后，蚀刻第一沟槽下面的衬底，以将第一沟槽的深度从第一深度延伸到第三深度。 最后，绝缘材料填充具有第三深度的第一沟槽以形成本发明的绝缘体。

公开(公告)号：US08148766B2

公开(公告)日：2012-04-03

申请号：US12244295

申请日：2008-10-02

Applicant: Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/3185 ,  H01L29/42324 ,  H01L29/66825

Abstract: A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed.

Abstract translation: 提供非易失性存储单元。 提供半导体衬底。 导电层和间隔层顺序地设置在半导体衬底之上。 在导电层和间隔层中限定具有底部和多个侧表面的至少一个沟槽。 第一氧化物层形成在沟槽的底部。 在第一氧化物层，间隔层和沟槽的多个侧表面上形成介电层。 在沟槽中形成第一多晶硅层。 并且去除间隔层上的电介质层的第一部分，从而形成用于非易失性存储单元的基本结构。

公开(公告)号：US20120012907A1

公开(公告)日：2012-01-19

申请号：US12874232

申请日：2010-09-02

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

IPC: H01L27/108

CPC classification number: H01L29/4983 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10882 ,  H01L29/4236

Abstract: A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.

Abstract translation: 公开了一种存储器布局结构，其中每个有效区域和每行有效区域的长度方向形成不等于零且不等于90度的夹角，位线和字线在有效区域之上彼此交叉 位线各自设置在有效区域的一行之上，位线接触插塞或节点接触插塞可以各自完全设置在源极/漏极区域上，或者部分地设置在源极/漏极区域上，并且部分地沿着侧壁向下延伸 （边缘壁），以执行侧壁接触。 自对准节点接触插头各自设置在两个相邻位线之间和两个相邻字线之间。

公开(公告)号：US07972924B2

公开(公告)日：2011-07-05

申请号：US12839387

申请日：2010-07-19

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/336

CPC classification number: H01L27/11521

Abstract: A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.

Abstract translation: 一种用于制造存储器的方法，包括首先提供具有水平相邻的控制栅极区域和浮置栅极区域的衬底，该栅极区域包括牺牲层和牺牲侧壁，去除牺牲层和牺牲侧壁以露出衬底，形成邻近控制的电介质侧壁 栅极区域，在暴露的衬底上形成浮栅电介质层，并形成与电介质侧壁相邻的浮栅极和浮置栅极电介质层。

公开(公告)号：US20110084325A1

公开(公告)日：2011-04-14

申请号：US12649361

申请日：2009-12-30

Applicant: Hsiao-Lei Wang ,  Chung-Lin Huang ,  Hung-Chang Liao ,  Shih-Lung Chen

Inventor： Hsiao-Lei Wang ,  Chung-Lin Huang ,  Hung-Chang Liao ,  Shih-Lung Chen

IPC: H01L27/108 ,  H01L21/762

CPC classification number: H01L27/10894 ,  H01L21/76229 ,  H01L27/10897

Abstract: An oxide spacer for stack DRAM gate stack is described, including: a semiconductor substrate with a memory array region and a periphery region, a plurality of gates disposed within the memory array region and the periphery region respectively, a silicon oxide spacer disposed on the gates, where the polysilicon contact plugs are formed by polysilicon deposition and chemical mechanical polish. After polysilicon contact plugs are formed, a silicon oxide layer is deposited to isolate the contacts and gate. The silicon oxide layer on top of contact plug is removed by chemical mechanical polish achieve planarization.

Abstract translation: 描述了一种用于堆叠DRAM栅极堆叠的氧化物间隔物，包括：具有存储器阵列区域和外围区域的半导体衬底，分别设置在存储器阵列区域和外围区域内的多个栅极，设置在栅极上的氧化硅间隔物 其中多晶硅接触插塞通过多晶硅沉积和化学机械抛光形成。 在形成多晶硅接触塞之后，沉积氧化硅层以隔离触点和栅极。 通过化学机械抛光去除接触塞顶部的氧化硅层，实现平面化。

公开(公告)号：US07855124B2

公开(公告)日：2010-12-21

申请号：US12035529

申请日：2008-02-22

Applicant: Hung-Ming Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Ming Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/76

CPC classification number: H01L21/823437 ,  H01L21/28273 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/11521

Abstract: A method for forming a semiconductor device, includes the steps of providing a substrate; forming a patterned stack on the substrate including a first dielectric layer on the substrate, a first conductive layer on the first dielectric layer and a mask layer on the first conductive layer, wherein a width of the mask layer is smaller than a width of the first conductive layer; forming a second dielectric layer on the sidewall of the patterned stack; forming a third dielectric layer on the substrate; forming a second conductive layer over the substrate; and removing the mask layer and a portion of the first conductive layer covered by the mask layer to form an opening so as to partially expose the first conductive layer.

Abstract translation: 一种形成半导体器件的方法，包括以下步骤：提供衬底; 在所述衬底上形成图案化的叠层，所述衬底上包括在所述衬底上的第一电介质层，所述第一电介质层上的第一导电层和所述第一导电层上的掩模层，其中所述掩模层的宽度小于所述第一导电层的宽度 导电层; 在所述图案化叠层的侧壁上形成第二电介质层; 在所述基板上形成第三电介质层; 在所述衬底上形成第二导电层; 以及去除所述掩模层和由所述掩模层覆盖的所述第一导电层的一部分以形成开口以部分地暴露所述第一导电层。

公开(公告)号：US20100279499A1

公开(公告)日：2010-11-04

申请号：US12839387

申请日：2010-07-19

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/8247

CPC classification number: H01L27/11521

Abstract: A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.

Abstract translation: 一种用于制造存储器的方法，包括首先提供具有水平相邻的控制栅极区域和浮置栅极区域的衬底，该栅极区域包括牺牲层和牺牲侧壁，去除牺牲层和牺牲侧壁以露出衬底，形成邻近控制的电介质侧壁 栅极区域，在暴露的衬底上形成浮栅电介质层，并形成与电介质侧壁相邻的浮栅极和浮置栅极电介质层。

公开(公告)号：US07781804B2

公开(公告)日：2010-08-24

申请号：US12101164

申请日：2008-04-11

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L29/80

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

Abstract: A non-volatile memory disposed on a substrate includes active regions, a memory array, and contacts. The active regions defined by isolation structures disposed in the substrate are extended in a first direction. The memory array is disposed on the substrate and includes memory cell columns, control gate lines and select gate lines. Each of the memory cell columns includes memory cells connected to one another in series and a source/drain region disposed in the substrate outside the memory cells. The contacts are disposed on the substrate at a side of the memory array and arranged along a second direction. The second direction crosses over the first direction. Each of the contacts extends across the isolation structures and connects the source/drain regions in the substrate at every two of the adjacent active regions.

Abstract translation: 设置在基板上的非易失性存储器包括有源区，存储器阵列和触点。 由设置在基板中的隔离结构限定的有源区域沿第一方向延伸。 存储器阵列设置在衬底上，并且包括存储单元列，控制栅极线和选择栅极线。 每个存储单元列包括彼此串联的存储单元和设置在存储单元外部的衬底中的源/漏区。 触点在存储器阵列的一侧设置在衬底上，并沿第二方向布置。 第二个方向穿过第一个方向。 每个触点延伸穿过隔离结构，并且在每个相邻的活性区域的每两个处连接衬底中的源极/漏极区域。

公开(公告)号：US20100013062A1

公开(公告)日：2010-01-21

申请号：US12244295

申请日：2008-10-02

Applicant: Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L23/58 ,  H01L21/31

CPC classification number: H01L27/11521 ,  H01L21/3185 ,  H01L29/42324 ,  H01L29/66825

Abstract: A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed.

Abstract translation: 提供非易失性存储单元。 提供半导体衬底。 导电层和间隔层顺序地设置在半导体衬底之上。 在导电层和间隔层中限定具有底部和多个侧表面的至少一个沟槽。 第一氧化物层形成在沟槽的底部。 在第一氧化物层，间隔层和沟槽的多个侧表面上形成介电层。 在沟槽中形成第一多晶硅层。 并且去除间隔层上的电介质层的第一部分，从而形成用于非易失性存储单元的基本结构。