公开(公告)号：US06486529B2

公开(公告)日：2002-11-26

申请号：US10066512

申请日：2002-02-04

申请人： Min-Hwa Chi ,  Chia-Shiung Tsai ,  Yeur-Luen Tu

发明人： Min-Hwa Chi ,  Chia-Shiung Tsai ,  Yeur-Luen Tu

IPC分类号： H01L218242

CPC分类号： H01L23/5223 ,  H01L23/5227 ,  H01L27/08 ,  H01L28/10 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A new method and structure is provided for the simultaneous creation of inductive and capacitive components in a monolithic substrate. The invention provides a method and structure whereby a vertical spiral inductor is created on the surface of a substrate. Multiple capacitors are created inside the coils of the vertical spiral conductor. A base layer of dielectric is deposited over the surface of a semiconductor substrate, contact plugs are provided in the base layer of dielectric. Multiple layers of dielectric are deposited over the surface of the base layer, layers of coils are created in the multiple layers of dielectric. Vias are provided in the layer of dielectric to interconnect overlying coils of the spiral inductor. An etch stop layer is deposited on the surface of the upper layer of dielectric. At least two openings are etched in the multiple layers of dielectric, these at least two openings are surrounded by the coils of the spiral inductor and align with the contact plugs provided in the base layers. Spacers are formed on the sidewalls of the openings, the bottom electrode layer, dielectric layer and top electrode layer of the at least two capacitors are deposited over the spacers. The openings are filled with a conductive material, the surface of the conductive material is polished down to the surface of the etch stop.

公开(公告)号：US06171923B2

公开(公告)日：2001-01-09

申请号：US09379228

申请日：1999-08-23

申请人： Min-Hwa Chi ,  Chih-Yuan Lu

发明人： Min-Hwa Chi ,  Chih-Yuan Lu

IPC分类号： H01L2120

CPC分类号： H01L27/1087 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/1203

摘要： A method for fabricating a DRAM cell, on a SOI layer, is described, featuring the incorporation of a two dimensional, trench capacitor structure, for increased DRAM cell signal, and the use of a polysilicon storage node structure to connect the SOI layer to the semiconductor substrate, to eliminate a floating body effect. A two dimensional trench is created by initially forming a vertical trench, through the SOI layer, through the underlying insulator layer, and into the semiconductor substrate. An isotropic etch is than performed to laterally remove a specific amount of insulator layer, exposed in the vertical trench, creating the lateral component of the two dimensional trench. A deposited polysilicon layer, coating the sides of the two dimensional trench, is used as the storage node structure, for the two dimensional, trench capacitor structure, while also connecting the SOI layer to the semiconductor substrate.

摘要翻译： 描述了在SOI层上制造DRAM单元的方法，其特征在于结合用于增加的DRAM单元信号的二维沟槽电容器结构，以及使用多晶硅存储节点结构将SOI层连接到 半导体衬底，消除浮体效应。 通过初始形成穿过SOI层的垂直沟槽，穿过下面的绝缘体层并进入半导体衬底而形成二维沟槽。 进行各向同性蚀刻以横向移除在垂直沟槽中暴露的特定量的绝缘体层，产生二维沟槽的横向分量。 作为二维沟槽电容器结构的存储节点结构，同时也将SOI层与半导体基板连接，使用涂覆二维沟槽的侧面的沉积多晶硅层。

公开(公告)号：US6111925A

公开(公告)日：2000-08-29

申请号：US47541

申请日：1998-03-25

申请人： Min-Hwa Chi

发明人： Min-Hwa Chi

IPC分类号： H03K5/135 ,  H04L7/033 ,  H04L7/00 ,  H03L7/00

CPC分类号： H03K5/135

摘要： A timing signal synchronization circuit to align an internal timing clock within an integrated circuit with an external system clock with minimum skew and within one cycle of the external system clock is disclosed. A timing signal synchronization circuit has an input buffer subcircuit to receive and delay the external system clock. A fixed delay line circuit is connected to the input buffer subcircuit to delay the received external system clock by a second delay factor to create a first timing signal. The first timing signal is the input to a first and a second measurement delay line. Each will respectively measure a first part and a second part of a period of the first timing signal. A first latch array will receive the measurement and create a first latch signal. A second latch array will receive the measurement and create a second latch signal. A variable delay line will receive the first and second latch signals, and adjust a delay time to values of the measurements of the first and second parts of the period of the first timing signal less the second delay factor. The variable delay line will receive and delay the first timing signal by the delay time to create a second timing signal. An internal buffer subcircuit will receive, buffer, amplify, and delay by a third delay factor the second timing signal to create the internal timing clock that is synchronized with the external system clock.

摘要翻译： 公开了一种定时信号同步电路，用于将集成电路内的内部定时时钟与具有最小偏移的外部系统时钟并在外部系统时钟的一个周期内对准。 定时信号同步电路具有用于接收和延迟外部系统时钟的输入缓冲器子电路。 固定的延迟线电路连接到输入缓冲器子电路，以将接收的外部系统时钟延迟第二延迟因子以产生第一定时信号。 第一定时信号是到第一和第二测量延迟线的输入。 每个将分别测量第一定时信号的周期的第一部分和第二部分。 第一个锁存阵列将接收测量并产生第一个锁存信号。 第二个锁存阵列将接收测量并产生第二个锁存信号。 可变延迟线将接收第一和第二锁存信号，并且将延迟时间调整到第一定时信号的周期的第一和第二部分的测量值减去第二延迟因子。 可变延迟线将接收并延迟第一定时信号延迟时间以产生第二定时信号。 内部缓冲器分支电路将接收，缓冲，放大和延迟第三个延迟因子第二定时信号，以创建与外部系统时钟同步的内部定时时钟。

公开(公告)号：US6016279A

公开(公告)日：2000-01-18

申请号：US050212

申请日：1998-03-30

申请人： Min-Hwa Chi

发明人： Min-Hwa Chi

IPC分类号： G11C7/06 ,  G11C7/12 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C7/06

摘要： A pre-charge and isolation circuit for a folded bit line DRAM array to reduce noise coupling between adjacent bit lines of a DRAM array by allowing only one bit line to be connected to a sense amplifier, while the complementary bit line remains at a reference voltage level is disclosed. The isolation pre-charge circuit will be connected to a pair of bit lines within a DRAM array to pre-charge portions the pair of bit lines to a reference voltage level and to connect a selected DRAM cell to a latching sense amplifier.

摘要翻译： 用于折叠位线DRAM阵列的预充电和隔离电路，用于通过仅允许一个位线连接到读出放大器来减少DRAM阵列的相邻位线之间的噪声耦合，而互补位线保持在参考电压 级别被披露。 隔离预充电电路将连接到DRAM阵列内的一对位线，以将该对位线的部分预充电到参考电压电平，并将选定的DRAM单元连接到锁存读出放大器。

公开(公告)号：US5909619A

公开(公告)日：1999-06-01

申请号：US18623

申请日：1998-02-04

申请人： Min-Hwa Chi

发明人： Min-Hwa Chi

IPC分类号： G11C11/56 ,  H01L27/108 ,  H01L21/8242

CPC分类号： G11C11/565 ,  H01L27/108

摘要： A DRAM cell capable of storing two bits of digital data as four levels of stored charge within the DRAM cell is disclosed. The four level DRAM cell has a pass transistor, a trench capacitor, and a stack capacitor. The pass transistors has a source connected to a bit line voltage generator to control placement of the charge within the four level DRAM cell, a gate connected to a word line voltage generator to control activation of the DRAM cells, and a drain. The trench capacitor has a top plate connected to the drain and a bottom plate connected to a substrate biasing voltage source. The stack capacitor has a first plate connected to the drain and a second plate connected to a coupling-gate voltage generator. The coupling-gate voltage generator will provide four levels of voltage that will indicate the level of charge to be stored within the four level DRAM cell. An interconnecting block that will interconnect the top plate of the trench capacitor to the first plate of the stack capacitor. The interconnection point between the trench capacitor and the stack capacitor will form the storage node that will retain the level of charge that indicates the state of the two bits of digital data. Four level DRAM cells will be arranged in a plurality of rows and columns to form an array of four level DRAM cells.

摘要翻译： 公开了能够将两比特数字数据存储在DRAM单元内的四级存储电荷的DRAM单元。 四级DRAM单元具有传输晶体管，沟槽电容器和堆叠电容器。 传输晶体管具有连接到位线电压发生器的源，以控制四电平DRAM单元内的电荷的放置，连接到字线电压发生器的栅极以控制DRAM单元的激活和漏极。 沟槽电容器具有连接到漏极的顶板和连接到衬底偏置电压源的底板。 堆叠电容器具有连接到漏极的第一板和连接到耦合栅电压发生器的第二板。 耦合栅极电压发生器将提供四个电平，其将指示要存储在四电平DRAM单元内的电荷电平。 互连块，其将沟槽电容器的顶板与堆叠电容器的第一板互连。 沟槽电容器和堆叠电容器之间的互连点将形成存储节点，其将保持指示两位数字数据的状态的电荷电平。 四级DRAM单元将被布置成多行和列以形成四级DRAM单元的阵列。

公开(公告)号：US5734191A

公开(公告)日：1998-03-31

申请号：US696065

申请日：1996-08-13

申请人： Min-Hwa Chi ,  Albert Bergemont ,  Carver Mead

发明人： Min-Hwa Chi ,  Albert Bergemont ,  Carver Mead

IPC分类号： H01L27/146 ,  H01L31/11 ,  H01L31/06

CPC分类号： H01L27/14681 ,  H01L31/1105

摘要： A contactless capacitor coupled bipolar phototransistor having an integrated electronic shutter for reducing the overflow and blooming problems associated with the imaging of strong images. Overflow control and an anti-blooming mechanism are obtained by use of a second emitter (the "shutter") which is used to remove excess image generated charge. This prevents the base-emitter junction potential from becoming forward biased during image integration when the phototransistor is exposed to a strong image. The shutter is biased slightly lower than the first emitter of the phototransistor so that the base-shutter junction is forward biased sooner than the base-emitter junction when the imaging element is exposed to a strong image. The overflow current of the generated holes is then drained to the shutter, rather than into the emitter where it would produce noise on the column sense line.

摘要翻译： 具有集成电子快门的非接触电容器耦合双极光电晶体管，用于减少与强图像成像有关的溢出和开花问题。 通过使用用于去除多余图像产生的电荷的第二发射器（“快门”）来获得溢流控制和防喷射机制。 这样就可以防止在光电晶体管暴露于强影像时图像积分期间基极 - 发射极结电位变得正向偏置。 快门被偏置成比光电晶体管的第一发射极略低，以便当成像元件暴露于强影像时，基极 - 快门结点比基极 - 发射极结更早地向前偏置。 所产生的孔的溢流电流然后被排放到快门，而不是进入发射器，在那里它会在列感测线上产生噪声。

公开(公告)号：US08574927B2

公开(公告)日：2013-11-05

申请号：US13335882

申请日：2011-12-22

申请人： Min-Hwa Chi ,  Xiufeng Han ,  Guoqiang Yu

发明人： Min-Hwa Chi ,  Xiufeng Han ,  Guoqiang Yu

IPC分类号： H01L21/8246

CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L43/08

摘要： Using a damascene process, a cup-shaped MTJ device is formed in an opening within a dielectric layer. A passivation layer is formed on the top surfaces of the sidewalls of the cup-shaped MTJ device to enclose the top of the sidewalls, thereby reducing magnetic flux leakage. Accordingly, the MTJ device may be fabricated using the same equipment that are compatible with and commonly used in CMOS technologies/processes.

摘要翻译： 使用镶嵌工艺，在电介质层内的开口中形成杯形MTJ器件。 在杯形MTJ装置的侧壁的顶表面上形成钝化层以封闭侧壁的顶部，由此减小磁通量泄漏。 因此，可以使用与CMOS技术/工艺中兼容并且通常使用的相同设备来制造MTJ器件。

公开(公告)号：US20130270641A1

公开(公告)日：2013-10-17

申请号：US13445428

申请日：2012-04-12

申请人： Min-Hwa Chi

发明人： Min-Hwa Chi

IPC分类号： H01L27/12 ,  H01L21/20

CPC分类号： H01L21/823821 ,  H01L29/1054 ,  H01L29/66818

摘要： Disclosed herein are various methods of forming FinFET semiconductor devices so as to tune the threshold voltage of such devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate to define at least one fin (or fins) for the device, prior to forming a gate structure above the fin (or fins), performing a first epitaxial growth process to grow a first semiconductor material on exposed portions of the fin (or fins) and forming the gate structure above the first semiconductor material on the fin (or fins).

摘要翻译： 本文公开了形成FinFET半导体器件的各种方法，以调节这些器件的阈值电压。 在一个示例中，该方法包括在半导体衬底内形成多个间隔开的沟槽，以在形成鳍片（或鳍片）之上的栅极结构之前，为器件限定至少一个翅片（或鳍片），执行第一 外延生长工艺以在翅片（或翅片）的暴露部分上生长第一半导体材料，并在翅片（或翅片）上的第一半导体材料上方形成栅极结构。

公开(公告)号：US20130099335A1

公开(公告)日：2013-04-25

申请号：US13335882

申请日：2011-12-22

申请人： Min-Hwa Chi ,  Xiufeng Han ,  Guoqiang Yu

发明人： Min-Hwa Chi ,  Xiufeng Han ,  Guoqiang Yu

IPC分类号： H01L29/82 ,  H01L21/8246

CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L43/08

摘要： Using a damascene process, a cup-shaped MTJ device is formed in an opening within a dielectric layer. A passivation layer is formed on the top surfaces of the sidewalls of the cup-shaped MTJ device to enclose the top of the sidewalls, thereby reducing magnetic flux leakage. Accordingly, the MTJ device may be fabricated using the same equipment that are compatible with and commonly used in CMOS technologies/processes.

摘要翻译： 使用镶嵌工艺，在电介质层内的开口中形成杯形MTJ器件。 在杯形MTJ装置的侧壁的顶表面上形成钝化层以封闭侧壁的顶部，由此减小磁通量泄漏。 因此，可以使用与CMOS技术/工艺中兼容并且通常使用的相同设备来制造MTJ器件。

公开(公告)号：US08273639B2

公开(公告)日：2012-09-25

申请号：US12132459

申请日：2008-06-03

申请人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

发明人： Hua Ji ,  Min-Hwa Chi ,  Fumitake Mieno

IPC分类号： H01L21/20

CPC分类号： C23C16/04 ,  C23C16/45527 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28282 ,  H01L21/3141 ,  H01L21/31616 ,  H01L21/3185

摘要： Disclosed are atomic layer deposition method and a semiconductor device including the atomic layer, including the steps: placing a semiconductor substrate in an atomic layer deposition chamber; feeding a first precursor gas to the semiconductor substrate within the chamber to form a first discrete monolayer on the semiconductor substrate; feeding an inert purge gas to the semiconductor substrate within the chamber to remove the first precursor gas which has not formed the first discrete monolayer on the semiconductor substrate; feeding a second precursor gas to the chamber to react with the first precursor gas which has formed the first discrete monolayer, forming a discrete atomic size islands; and feeding an inert purge gas to the semiconductor substrate within the chamber to remove the second precursor gas which has not reacted with the first precursor gas and byproducts produced by the reaction between the first and the second precursor gases.

摘要翻译： 公开了原子层沉积方法和包括原子层的半导体器件，包括以下步骤：将半导体衬底放置在原子层沉积室中; 将第一前体气体供给到腔室内的半导体衬底，以在半导体衬底上形成第一离散单层; 向腔室内的半导体衬底供给惰性清洗气体以去除在半导体衬底上未形成第一离散单层的第一前体气体; 将第二前体气体供给到所述室中以与形成所述第一离散单层的所述第一前体气体反应，形成离散的原子尺寸岛; 以及将惰性吹扫气体供给到室内的半导体衬底以除去未与第一前体气体反应的第二前体气体和由第一和第二前体气体之间的反应产生的副产物。